Simulation Results: clkmgr

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.91 %
  • code
  • 98.66 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.12 %
  • branch
  • 98.85 %
  • cond
  • 96.14 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.75%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.660s 207.868us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 0.850s 87.538us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 6.480s 1311.835us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.340s 78.262us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.570s 483.108us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
clkmgr_csr_aliasing 1.340s 78.262us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.130s 51.055us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.570s 297.644us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.340s 82.884us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.120s 98.886us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.660s 207.868us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 13.180s 2478.319us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 12.930s 2416.775us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 13.180s 2478.319us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 53.240s 11009.765us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.460s 229.849us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 2.960s 710.204us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 2.960s 710.204us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 0.850s 87.538us 5 5 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
clkmgr_csr_aliasing 1.340s 78.262us 5 5 100.00
clkmgr_same_csr_outstanding 2.130s 797.667us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 0.850s 87.538us 5 5 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
clkmgr_csr_aliasing 1.340s 78.262us 5 5 100.00
clkmgr_same_csr_outstanding 2.130s 797.667us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 20 25 80.00
clkmgr_tl_intg_err 3.160s 1059.820us 20 20 100.00
clkmgr_sec_cm 0.920s 42.166us 0 5 0.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 1.750s 154.801us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 1.750s 154.801us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 1.750s 154.801us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 1.750s 154.801us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.910s 599.181us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 3.160s 1059.820us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 13.180s 2478.319us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 12.930s 2416.775us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 1.750s 154.801us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.550s 172.536us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.290s 291.135us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.330s 214.885us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 46 50 92.00
clkmgr_clk_handshake_intersig_mubi 1.300s 87.567us 46 50 92.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.250s 105.375us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 0.920s 42.166us 0 5 0.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 0.920s 105.342us 20 20 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 0.920s 42.166us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 5.880s 2340.488us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 118.680s 46351.795us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 59715160995516143861652212294819455250160408710004789745838643613153179897054 104
UVM_ERROR @ 42166347 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 42166347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 65506372796876805492117775477766418909322874695827630288265343678298845701724 92
UVM_ERROR @ 43820969 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 43820969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 103253978571567065402620515934782271402402090438971162205830927864368640513547 74
UVM_ERROR @ 2513959 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 2513959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 53843936816281959201406642211777305592267916718641089238154804008727913862373 84
UVM_ERROR @ 33653099 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 33653099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 29073939359589186601897083288328810057573067159609925130572917275682284624976 79
UVM_ERROR @ 15662280 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 15662280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 104397096528012153879135441014528635702811657507707610638525118078247032099595 71
UVM_ERROR @ 13349548 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (1 [0x1] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 13349548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 4596019519810102402778582574253727188401849772679488361423115584149955407749 71
UVM_ERROR @ 31506806 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (12 [0xc] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 31506806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 58523691861917998599425234891378724568843382580499945530625073814466569914442 71
UVM_ERROR @ 29542156 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (0 [0x0] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 29542156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 36854759614081441267016501665904648325760987760734001982313477634076369219007 71
UVM_ERROR @ 3876242 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (1 [0x1] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 3876242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---