Simulation Results: csrng

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.43 %
  • code
  • 96.35 %
  • assert
  • 95.85 %
  • func
  • 91.09 %
  • block
  • 98.76 %
  • line
  • 99.64 %
  • branch
  • 96.88 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 4.000s 174.747us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 49.988us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 57.497us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 12.000s 276.834us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 6.000s 401.322us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 7.000s 529.415us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 57.497us 20 20 100.00
csrng_csr_aliasing 6.000s 401.322us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
alerts 500 500 100.00
csrng_alert 40.000s 3168.447us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 99.652us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 420.000s 44039.475us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 420.000s 44039.475us 50 50 100.00
stress_all 50 50 100.00
csrng_stress_all 1084.000s 97748.216us 50 50 100.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 35.204us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 12.000s 369.522us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 22.000s 2264.937us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 22.000s 2264.937us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 49.988us 5 5 100.00
csrng_csr_rw 3.000s 57.497us 20 20 100.00
csrng_csr_aliasing 6.000s 401.322us 5 5 100.00
csrng_same_csr_outstanding 5.000s 96.304us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 49.988us 5 5 100.00
csrng_csr_rw 3.000s 57.497us 20 20 100.00
csrng_csr_aliasing 6.000s 401.322us 5 5 100.00
csrng_same_csr_outstanding 5.000s 96.304us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_tl_intg_err 14.000s 1486.426us 20 20 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_config_regwen 70 70 100.00
csrng_csr_rw 3.000s 57.497us 20 20 100.00
csrng_regwen 3.000s 15.117us 50 50 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 40.000s 3168.447us 500 500 100.00
sec_cm_intersig_mubi 50 50 100.00
csrng_stress_all 1084.000s 97748.216us 50 50 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 40.000s 3168.447us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
sec_cm_constants_lc_gated 50 50 100.00
csrng_stress_all 1084.000s 97748.216us 50 50 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 40.000s 3168.447us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 14.000s 1486.426us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
csrng_sec_cm 9.000s 923.275us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 16.000s 803.211us 200 200 100.00
csrng_err 4.000s 99.652us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 1208.000s 106019.100us 10 10 100.00

Error Messages

   Test seed line log context