Simulation Results: edn

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.52 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.400s 20.979us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.960s 54.401us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.940s 26.829us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.830s 357.012us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.810s 110.930us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.660s 29.590us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.940s 26.829us 20 20 100.00
edn_csr_aliasing 1.810s 110.930us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 3.340s 625.676us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 3.340s 625.676us 300 300 100.00
genbits 300 300 100.00
edn_genbits 3.340s 625.676us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.550s 28.555us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.880s 319.554us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 23.392us 100 100 100.00
disable 100 100 100.00
edn_disable 1.370s 33.209us 50 50 100.00
edn_disable_auto_req_mode 1.980s 62.550us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 6.840s 558.705us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.990s 27.894us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.380s 122.680us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.150s 248.405us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.150s 248.405us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.960s 54.401us 5 5 100.00
edn_csr_rw 0.940s 26.829us 20 20 100.00
edn_csr_aliasing 1.810s 110.930us 5 5 100.00
edn_same_csr_outstanding 1.290s 185.513us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.960s 54.401us 5 5 100.00
edn_csr_rw 0.940s 26.829us 20 20 100.00
edn_csr_aliasing 1.810s 110.930us 5 5 100.00
edn_same_csr_outstanding 1.290s 185.513us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
edn_tl_intg_err 8.120s 759.300us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.000s 21.526us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.880s 319.554us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.880s 319.554us 200 200 100.00
edn_sec_cm 7.550s 772.543us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.880s 319.554us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 8.120s 759.300us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 121.060s 9753.412us 50 50 100.00

Error Messages

   Test seed line log context