Simulation Results: edn

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 95.95 %
  • assert
  • 97.14 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.300s 17.273us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.180s 19.947us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.130s 14.825us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 5.460s 263.303us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.550s 42.465us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.970s 102.195us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.130s 14.825us 20 20 100.00
edn_csr_aliasing 1.550s 42.465us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.040s 178.546us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.040s 178.546us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.040s 178.546us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.380s 22.058us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.620s 98.972us 200 200 100.00
errs 100 100 100.00
edn_err 1.530s 69.258us 100 100 100.00
disable 100 100 100.00
edn_disable 1.260s 17.424us 50 50 100.00
edn_disable_auto_req_mode 1.710s 40.090us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 5.690s 643.519us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.280s 31.392us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.470s 44.730us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.780s 523.005us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.780s 523.005us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.180s 19.947us 5 5 100.00
edn_csr_rw 1.130s 14.825us 20 20 100.00
edn_csr_aliasing 1.550s 42.465us 5 5 100.00
edn_same_csr_outstanding 1.610s 140.769us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.180s 19.947us 5 5 100.00
edn_csr_rw 1.130s 14.825us 20 20 100.00
edn_csr_aliasing 1.550s 42.465us 5 5 100.00
edn_same_csr_outstanding 1.610s 140.769us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 4.360s 264.234us 20 20 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.280s 19.233us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.620s 98.972us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.620s 98.972us 200 200 100.00
edn_sec_cm 3.960s 600.448us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.620s 98.972us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.360s 264.234us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 99.990s 5820.762us 50 50 100.00

Error Messages

   Test seed line log context