flash_ctrl Simulation Results

Simulation Results: flash_ctrl

25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.91 %

code
95.62 %

assert
96.71 %

func
98.39 %

line
96.08 %

branch
97.41 %

cond
94.78 %

toggle
98.66 %

FSM
91.16 %

Validation stages

V1		100.00%
V2		99.03%
V2S		99.76%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	136.550s	41.249us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	23.090s	120.814us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	42.080s	117.173us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	91.010s	12774.905us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	57.410s	3316.730us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	17.180s	387.303us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
	flash_ctrl_csr_aliasing	57.410s	3316.730us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	10.980s	18.495us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	10.710s	33.912us	5	5	100.00

1125/1136 passed

99.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	25.150s	29.647us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	94.670s	274.566us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1887.450s	334109.288us	3	3	100.00
	flash_ctrl_hw_rma_reset	788.320s	130178.928us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.860s	139.004us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2349.440s	305494.141us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	341.020s	18636.118us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	226.950s	41555.047us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	4965.400s	978145.257us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	85.550s	3037.045us	5	5	100.00
rd_buff_eviction_w_ecc				97	100	97.00
	flash_ctrl_rw_evict	32.610s	69.246us	38	40	95.00
	flash_ctrl_rw_evict_all_en	33.350s	92.349us	39	40	97.50
	flash_ctrl_re_evict	36.010s	81.624us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	203.870s	4588.151us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	203.870s	4588.151us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	738.510s	11602.776us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	28.140s	686.870us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	806.830s	872.049us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	715.370s	14366.835us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	724.420s	2520.945us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1303.190s	1173.567us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.210s	47.007us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	179.500s	2764.408us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.850s	22.218us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.530s	56.663us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	806.820s	315.938us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	231.620s	8252.288us	50	50	100.00
	flash_ctrl_otp_reset	113.080s	395.780us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1887.450s	334109.288us	3	3	100.00
interrupts				95	100	95.00
	flash_ctrl_intr_rd	183.000s	7667.912us	37	40	92.50
	flash_ctrl_intr_wr	80.460s	5479.766us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	345.570s	12743.994us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	526.600s	285710.475us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	77.420s	893.578us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	62.630s	1978.575us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	21.720s	23.628us	5	5	100.00
	flash_ctrl_ro_derr	139.170s	990.097us	10	10	100.00
	flash_ctrl_rw_derr	255.460s	3986.648us	10	10	100.00
	flash_ctrl_derr_detect	195.250s	3687.445us	5	5	100.00
	flash_ctrl_integrity	545.730s	4369.227us	5	5	100.00
single_bit_err				24	25	96.00
	flash_ctrl_read_word_sweep_serr	23.190s	343.555us	5	5	100.00
	flash_ctrl_ro_serr	118.050s	2542.351us	10	10	100.00
	flash_ctrl_rw_serr	212.560s	23754.169us	9	10	90.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	99.890s	12813.631us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	127.070s	1629.357us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	200.130s	7457.836us	19	20	95.00
	flash_ctrl_write_word_sweep	13.900s	150.831us	1	1	100.00
	flash_ctrl_read_word_sweep	11.670s	25.952us	1	1	100.00
	flash_ctrl_ro	112.410s	645.755us	20	20	100.00
	flash_ctrl_rw	566.420s	5037.049us	19	20	95.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	41.130s	709.183us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	1012.680s	159323.880us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	301.190s	10019.432us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	15.150s	69.453us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	11.570s	112.923us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	18.400s	66.476us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	18.400s	66.476us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.080s	117.173us	5	5	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
	flash_ctrl_csr_aliasing	57.410s	3316.730us	5	5	100.00
	flash_ctrl_same_csr_outstanding	31.830s	312.712us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.080s	117.173us	5	5	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
	flash_ctrl_csr_aliasing	57.410s	3316.730us	5	5	100.00
	flash_ctrl_same_csr_outstanding	31.830s	312.712us	20	20	100.00

V2S

821/823 passed

99.76 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	110.060s	310.221us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	535.500s	4854.800us	20	20	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	535.500s	4854.800us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	535.500s	4854.800us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	32.750s	209.557us	3	3	100.00
	flash_ctrl_wr_intg	11.990s	169.810us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	136.550s	41.249us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	113.080s	395.780us	80	80	100.00
	flash_ctrl_disable	22.850s	22.218us	50	50	100.00
	flash_ctrl_sec_info_access	103.610s	41143.887us	50	50	100.00
	flash_ctrl_connect	17.530s	56.663us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	13.540s	23.288us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.420s	28.392us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.680s	57.871us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.850s	22.218us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	32.750s	209.557us	3	3	100.00
	flash_ctrl_access_after_disable	9.250s	195.462us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	24.930s	130.212us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.850s	22.218us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	28.140s	686.870us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	566.420s	5037.049us	19	20	95.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	212.560s	23754.169us	9	10	90.00
	flash_ctrl_rw_derr	255.460s	3986.648us	10	10	100.00
	flash_ctrl_integrity	545.730s	4369.227us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1887.450s	334109.288us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	17.760s	668.742us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	12.530s	56.003us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	12.370s	24.373us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2134.780s	1087.942us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	29.860s	337.992us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	384.040s	1464.635us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes
	flash_ctrl_intr_wr	93594018765505277950570373945858068237334353286961242799345927189017740485832	None	Job timed out after 60 minutes
	flash_ctrl_intr_wr_slow_flash	47948211176861810638762576106702247862313528568067254207141076609403365726762	None	Job timed out after 60 minutes
	flash_ctrl_rw_serr	17856133542402880278425260959377123252386804205663856081396579786933642120518	None	Job timed out after 60 minutes
	flash_ctrl_rw	6681480252529872562917261665087095187080987803312136498314092313343722364943	None	Job timed out after 60 minutes
	flash_ctrl_wo	2807059117064486857271998132093196572104302471154151191897231866544912706099	None	Job timed out after 60 minutes
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp e_4ffc9037:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	109305322899196548938116050527470869568010021093124469106788026766205764002101	105	UVM_ERROR @ 4989437.9 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 6: obs:exp 8597252e_4ffc9037:ffffffff_ffffffff mismatch!! UVM_INFO @ 4989437.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	76474312938330889416485413915323876422943154007429413570992186117341013959932	105	UVM_ERROR @ 61347.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 61347.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	31729433922624167675158597499543017625886240050028316557369612074504444682891	105	UVM_ERROR @ 40443.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 40443.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	90063409969227424313015476042093443917720285952832738836548524991468243434587	105	UVM_ERROR @ 37380.6 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 37380.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp a0681a28_3a4e7741:ffffffff_3a4e mismatch!!
	flash_ctrl_intr_rd	4217944341443128117662321550745868605085380689429065959609657136327380054540	105	UVM_ERROR @ 3721014.1 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 4: obs:exp a0681a28_3a4e7741:ffffffff_3a4e7741 mismatch!! UVM_INFO @ 3721014.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp e1e31_*:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	76319606041768502669067312599213767413833558677637333922348515206234826585552	105	UVM_ERROR @ 2314575.9 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 7: obs:exp 206e1e31_13280000:ffffffff_ffffffff mismatch!! UVM_INFO @ 2314575.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---