Simulation Results: hmac

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.80 %
  • code
  • 99.25 %
  • assert
  • 97.14 %
  • func
  • 100.00 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.80 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.800s 850.476us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 0.880s 163.411us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 0.960s 97.665us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 11.080s 7624.592us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 5.970s 1627.001us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 871.340s 499485.527us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 0.960s 97.665us 20 20 100.00
hmac_csr_aliasing 5.970s 1627.001us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 53.430s 3545.617us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 88.130s 1674.299us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 288.160s 8112.939us 30 30 100.00
hmac_test_sha384_vectors 562.710s 31505.417us 75 75 100.00
hmac_test_sha512_vectors 553.590s 15485.169us 75 75 100.00
hmac_test_hmac256_vectors 15.870s 766.256us 50 50 100.00
hmac_test_hmac384_vectors 17.570s 408.576us 60 60 100.00
hmac_test_hmac512_vectors 17.470s 1496.458us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 42.660s 3285.928us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1342.710s 51605.099us 10 10 100.00
error 10 10 100.00
hmac_error 49.320s 17720.387us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 116.950s 18721.735us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.800s 850.476us 10 10 100.00
hmac_long_msg 53.430s 3545.617us 10 10 100.00
hmac_back_pressure 88.130s 1674.299us 25 25 100.00
hmac_datapath_stress 1342.710s 51605.099us 10 10 100.00
hmac_burst_wr 42.660s 3285.928us 50 50 100.00
hmac_stress_all 1756.830s 191440.527us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.800s 850.476us 10 10 100.00
hmac_long_msg 53.430s 3545.617us 10 10 100.00
hmac_back_pressure 88.130s 1674.299us 25 25 100.00
hmac_datapath_stress 1342.710s 51605.099us 10 10 100.00
hmac_wipe_secret 116.950s 18721.735us 10 10 100.00
hmac_test_sha256_vectors 288.160s 8112.939us 30 30 100.00
hmac_test_sha384_vectors 562.710s 31505.417us 75 75 100.00
hmac_test_sha512_vectors 553.590s 15485.169us 75 75 100.00
hmac_test_hmac256_vectors 15.870s 766.256us 50 50 100.00
hmac_test_hmac384_vectors 17.570s 408.576us 60 60 100.00
hmac_test_hmac512_vectors 17.470s 1496.458us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.800s 850.476us 10 10 100.00
hmac_long_msg 53.430s 3545.617us 10 10 100.00
hmac_back_pressure 88.130s 1674.299us 25 25 100.00
hmac_datapath_stress 1342.710s 51605.099us 10 10 100.00
hmac_burst_wr 42.660s 3285.928us 50 50 100.00
hmac_error 49.320s 17720.387us 10 10 100.00
hmac_wipe_secret 116.950s 18721.735us 10 10 100.00
hmac_test_sha256_vectors 288.160s 8112.939us 30 30 100.00
hmac_test_sha384_vectors 562.710s 31505.417us 75 75 100.00
hmac_test_sha512_vectors 553.590s 15485.169us 75 75 100.00
hmac_test_hmac256_vectors 15.870s 766.256us 50 50 100.00
hmac_test_hmac384_vectors 17.570s 408.576us 60 60 100.00
hmac_test_hmac512_vectors 17.470s 1496.458us 75 75 100.00
hmac_stress_all 1756.830s 191440.527us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1756.830s 191440.527us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.960s 15.584us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.710s 13.874us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.200s 208.097us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.200s 208.097us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 0.880s 163.411us 5 5 100.00
hmac_csr_rw 0.960s 97.665us 20 20 100.00
hmac_csr_aliasing 5.970s 1627.001us 5 5 100.00
hmac_same_csr_outstanding 1.910s 120.180us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 0.880s 163.411us 5 5 100.00
hmac_csr_rw 0.960s 97.665us 20 20 100.00
hmac_csr_aliasing 5.970s 1627.001us 5 5 100.00
hmac_same_csr_outstanding 1.910s 120.180us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 3.280s 1076.566us 20 20 100.00
hmac_sec_cm 1.330s 215.826us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 3.280s 1076.566us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.800s 850.476us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.770s 139.928us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 471.740s 79233.320us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.790s 19.380us 1 1 100.00

Error Messages

   Test seed line log context