Simulation Results: keymgr

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 98.60 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.09 %
  • branch
  • 98.92 %
  • cond
  • 98.18 %
  • toggle
  • 99.16 %
  • FSM
  • 97.67 %
Validation stages
V1
99.44%
V2
99.17%
V2S
99.51%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
keymgr_smoke 28.500s 4019.107us 49 50 98.00
random 50 50 100.00
keymgr_random 48.380s 3828.715us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.400s 509.715us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 11.650s 4610.841us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 6.370s 1215.255us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.250s 45.793us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_csr_aliasing 6.370s 1215.255us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 48 50 96.00
keymgr_cfg_regwen 42.240s 2461.875us 48 50 96.00
sideload 199 200 99.50
keymgr_sideload 44.890s 15585.400us 50 50 100.00
keymgr_sideload_kmac 51.240s 6696.262us 49 50 98.00
keymgr_sideload_aes 48.110s 6343.780us 50 50 100.00
keymgr_sideload_otbn 42.290s 1694.113us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 21.790s 1965.421us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 9.740s 1268.566us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 11.530s 1220.789us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 51.850s 7879.219us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 26.090s 5632.943us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 26.910s 4724.491us 50 50 100.00
stress_all 47 50 94.00
keymgr_stress_all 659.890s 88387.732us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 1.090s 17.614us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.350s 17.321us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.040s 559.411us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.040s 559.411us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.400s 509.715us 5 5 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_csr_aliasing 6.370s 1215.255us 5 5 100.00
keymgr_same_csr_outstanding 3.250s 140.815us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.400s 509.715us 5 5 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_csr_aliasing 6.370s 1215.255us 5 5 100.00
keymgr_same_csr_outstanding 3.250s 140.815us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 8.360s 5279.114us 20 20 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.900s 305.435us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.900s 305.435us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.900s 305.435us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.900s 305.435us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.390s 426.520us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.360s 5279.114us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.900s 305.435us 20 20 100.00
sec_cm_op_config_regwen 48 50 96.00
keymgr_cfg_regwen 42.240s 2461.875us 48 50 96.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_random 48.380s 3828.715us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_random 48.380s 3828.715us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.710s 40.299us 20 20 100.00
keymgr_random 48.380s 3828.715us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 9.740s 1268.566us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 26.090s 5632.943us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 26.090s 5632.943us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 48.380s 3828.715us 50 50 100.00
sec_cm_output_keys_ctrl_redun 49 50 98.00
keymgr_sideload_protect 27.130s 2044.405us 49 50 98.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 34.900s 5141.305us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 9.740s 1268.566us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.900s 5141.305us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.900s 5141.305us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.900s 5141.305us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.590s 2401.196us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 34.900s 5141.305us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 50 40.00
keymgr_stress_all_with_rand_reset 16.570s 979.672us 20 50 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 39635741723383837134154926196241423776305610994030386800312735336157503998160 1621
UVM_ERROR @ 7310049098 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7310049098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 77445343587487145255226699074689118179192023641926367111629241356948201074395 199
UVM_ERROR @ 227931624 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 227931624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45185930860212168064384992520285389265121999751714149536085939036291272601448 802
UVM_ERROR @ 1412013131 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1412013131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40001004001342481875101188354130522282070146067537587019443293953517731882429 125
UVM_ERROR @ 107538789 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107538789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 67189075371443803546860037630727524474190830716197348593842614438935262364394 2384
UVM_ERROR @ 3519085929 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3519085929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 81580481653959297952905259802517486887271374088112370482173782211220736164718 338
UVM_ERROR @ 331671918 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 331671918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17098116995213934272912686413667000306840381058745747673320947398784287892696 702
UVM_ERROR @ 228993722 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 228993722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 10284637612565977073950898644647758509055734025484524291439726687275570005311 468
UVM_ERROR @ 1007001774 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1007001774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51444809421909226261209019371739301445042429039819811453795951966699917251006 224
UVM_ERROR @ 679273594 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 679273594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17367180714972895712654836059351735020138271080082771190663133868665807492136 180
UVM_ERROR @ 472030440 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 472030440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 33382790145206941993264072761302245479780667281257737226322563129170701354997 640
UVM_ERROR @ 210916593 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 210916593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24245910895982885504809171919189002024022378524911407561996055427822353048529 715
UVM_ERROR @ 660254113 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 660254113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 82077941192261332228310724155308076305842126980592451621833967508718675985257 268
UVM_ERROR @ 251880851 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 251880851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1687138676902329304866129295025811512520264890094263250431086651896963230888 586
UVM_ERROR @ 234771250 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 234771250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 88243796909364114031714422332095595249977188610097326534439639009506019264362 171
UVM_ERROR @ 1642475135 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1642475135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56114353200154243808984227350231073370938033975389873364537867515574326989118 421
UVM_ERROR @ 211550261 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 211550261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 96390148788836789271501466840773152823072444094358052677032855301013854310380 696
UVM_ERROR @ 231359404 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 231359404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12002072802166603321765783467792730489368432311753501880913818642988758266347 361
UVM_ERROR @ 214351377 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 214351377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87559904971200731230622068137810906051347109340873888551047569144393205711022 649
UVM_ERROR @ 1228957025 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1228957025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40057308423468074631676494487073782159028363269674844083364151385660117399178 169
UVM_ERROR @ 144322352 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 144322352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28597780642921242507014017920626575111604528263056829581586090927064516364555 155
UVM_ERROR @ 494050485 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 494050485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94013037754632770674592012311802298168094427069689046117909818916537076764103 749
UVM_ERROR @ 617588838 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 617588838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 91720940547822493274178914833702041078959388089726593252834326620748937685718 298
UVM_ERROR @ 664565065 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 664565065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65406467622963980331353238209169324973699145340556542302999631563013175605199 159
UVM_ERROR @ 265324347 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 265324347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45659493430533040181955588737541316354603186182468694155451629982459079548960 1371
UVM_ERROR @ 501486423 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 501486423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99919434693549458119501621988995382067270426122872188417959205476799102781393 636
UVM_ERROR @ 137604728 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 137604728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63261208069790792831402991880721098548901427364907183269315497911416606489365 605
UVM_ERROR @ 444822702 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 444822702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80733551766520487191992779138132678306498647707725601053619564094236744255280 292
UVM_ERROR @ 495170080 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 495170080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_sideload_protect 71936198824252549226606594390811856937280912036756442771834065835056558017895 91
UVM_ERROR @ 15083029 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 15083029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 90736325093078506406101698280875034756579313320738947363633346559558423113996 4046
UVM_ERROR @ 2000515647 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2000515647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 79205191401241873275136314479150030904845740597761155044787533796074907645648 95
UVM_ERROR @ 13138360 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 13138360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload_kmac 92500235985650790780796996362631553984394255681533584980452917316493964282651 94
UVM_ERROR @ 26276297 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 26276297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 47598916921793282534005167393072105588541533453306818896472235060702777572374 507
UVM_ERROR @ 102064154 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 102064154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_smoke 78594017469558984225165079669147487255559371504108821038938352269210518351090 86
UVM_ERROR @ 2631237 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2631237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 53637534589824961857434851080880612652068151643911024099892225669518824172501 606
UVM_ERROR @ 130872712 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 130872712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_lc_disable 114972978138988670841995513503582331653501028300754747125049186952165890970693 271
UVM_ERROR @ 46465102 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (134395338 [0x802b5ca] vs 134395338 [0x802b5ca]) reg name: keymgr_reg_block.sw_share0_output_5
UVM_INFO @ 46465102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
keymgr_stress_all_with_rand_reset 71837696157520882042426569019316292541670693811856929247659306463775971589639 906
UVM_ERROR @ 469846765 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (13874405706610753186824878019936727972161756069395118412370487047808878818957747994445788202165707810123381995288592824110092936121498432888834552873256880362555780207486957208829378989190329538276586874866824074058472130513472528933641745597693514728266796842002261750132503002998340423000639001171237960786110899583240446352692982445801752306032 [0x3a101fb5000000000000000000000000000000000000000000000000000000009ba99e2a42ab23c37fe3f82ea0e6f44347890cfe7afc1717404720344165f5b159a65aad17fd2fdfa54f4c35f015a27ed4a2087d84092d2c18253e5b74c1e205843c3cfc57efa2472d1cc21f91a19ba369802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 2673976467685354449926784160613592515805919237028772903331587144937138464547262772035046066067862871401920783264215234871120571296281368907626086552638164780245227514992298006461006119809779907676131026569296786344777663659111608570897223415010226386019556812806012227563198108021970599932677345037884642009766716032897103971308256174448 [0x300fe3519b2264010000000000000000000000003a9a851a000000009ba99e2a42ab23c37fe3f82ea0e6f44347890cfe7afc1717404720344165f5b159a65aad17fd2fdfa54f4c35f015a27ed4a2087d84092d2c18253e5b74c1e205843c3cfc57efa2472d1cc21f91a19ba369802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0xd4a2087d84092d2c18253e5b74c1e205843c3cfc57efa2472d1cc21f91a19ba3, exp: 0xd4a2087d84092d2c18253e5b74c1e205843c3cfc57efa2472d1cc21f91a19ba3
HealthMeasurement act: 0x59a65aad17fd2fdfa54f4c35f015a27e, exp: 0x59a65aad17fd2fdfa54f4c35f015a27e
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_binding_regwen
keymgr_stress_all_with_rand_reset 13095601712458140298437203313909198252274172686880588750371450502838347581642 1179
UVM_ERROR @ 376450244 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.sw_binding_regwen
UVM_INFO @ 376450244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 58527650589696991879108663731169787266440063202885636440342219005836977371954 409
UVM_ERROR @ 150942162 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
UVM_INFO @ 150942162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---