Simulation Results: kmac

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.58 %
  • code
  • 94.04 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.20 %
  • branch
  • 97.08 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 79.260s 3345.298us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.960s 119.914us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.020s 33.326us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 12.340s 1007.440us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.160s 1912.703us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 1.970s 526.648us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.020s 33.326us 20 20 100.00
kmac_csr_aliasing 7.160s 1912.703us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.720s 42.565us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.350s 23.874us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3391.060s 115316.457us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1308.890s 27393.505us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2202.880s 861886.156us 5 5 100.00
kmac_test_vectors_sha3_256 2205.480s 331195.632us 5 5 100.00
kmac_test_vectors_sha3_384 30.800s 3936.407us 5 5 100.00
kmac_test_vectors_sha3_512 941.150s 19110.470us 5 5 100.00
kmac_test_vectors_shake_128 1807.980s 42348.170us 5 5 100.00
kmac_test_vectors_shake_256 2000.560s 59123.750us 5 5 100.00
kmac_test_vectors_kmac 3.030s 42.531us 5 5 100.00
kmac_test_vectors_kmac_xof 3.740s 113.507us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 425.640s 71080.456us 50 50 100.00
app 50 50 100.00
kmac_app 350.340s 18902.145us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 353.490s 50333.920us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 384.120s 15590.826us 50 50 100.00
error 50 50 100.00
kmac_error 472.540s 60431.133us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 22.900s 28459.913us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.460s 1054.487us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 51.810s 2403.779us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 2.950s 106.245us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 73.250s 33280.798us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 51.490s 1879.628us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2362.570s 32349.211us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.830s 15.604us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 18.586us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.070s 1099.941us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.070s 1099.941us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.960s 119.914us 5 5 100.00
kmac_csr_rw 1.020s 33.326us 20 20 100.00
kmac_csr_aliasing 7.160s 1912.703us 5 5 100.00
kmac_same_csr_outstanding 2.100s 128.099us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.960s 119.914us 5 5 100.00
kmac_csr_rw 1.020s 33.326us 20 20 100.00
kmac_csr_aliasing 7.160s 1912.703us 5 5 100.00
kmac_same_csr_outstanding 2.100s 128.099us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.040s 347.889us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.040s 347.889us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.040s 347.889us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.040s 347.889us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.160s 1703.474us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.220s 2301.425us 20 20 100.00
kmac_sec_cm 138.350s 11352.061us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.220s 2301.425us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 51.490s 1879.628us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 79.260s 3345.298us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 425.640s 71080.456us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.040s 347.889us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 138.350s 11352.061us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 138.350s 11352.061us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 138.350s 11352.061us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 79.260s 3345.298us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 51.490s 1879.628us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 138.350s 11352.061us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 372.270s 79141.083us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 79.260s 3345.298us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 298.500s 4728.724us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 79865290290605419699631907715109392761382141327692746923056789182482602764106 197
UVM_ERROR @ 3526513604 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3526513604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---