Simulation Results: kmac

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.35 %
  • code
  • 92.18 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.44 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.45%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 65.670s 5904.052us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.480s 40.303us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.430s 60.208us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 17.040s 1266.468us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.030s 492.225us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.840s 363.292us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.430s 60.208us 20 20 100.00
kmac_csr_aliasing 7.030s 492.225us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.080s 26.840us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.940s 241.555us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3524.190s 507606.231us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 973.100s 52083.212us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1899.880s 249365.021us 5 5 100.00
kmac_test_vectors_sha3_256 1714.890s 1077218.127us 5 5 100.00
kmac_test_vectors_sha3_384 1035.220s 13538.619us 5 5 100.00
kmac_test_vectors_sha3_512 893.120s 39572.257us 5 5 100.00
kmac_test_vectors_shake_128 2339.810s 211743.115us 5 5 100.00
kmac_test_vectors_shake_256 1455.940s 17086.277us 5 5 100.00
kmac_test_vectors_kmac 2.600s 99.346us 5 5 100.00
kmac_test_vectors_kmac_xof 2.430s 34.932us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 391.150s 16575.775us 50 50 100.00
app 50 50 100.00
kmac_app 328.620s 127901.736us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 182.840s 25159.973us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 339.460s 27981.206us 50 50 100.00
error 50 50 100.00
kmac_error 473.050s 14035.813us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.660s 40368.297us 50 50 100.00
sideload_invalid 37 50 74.00
kmac_sideload_invalid 124.180s 10044.310us 37 50 74.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 43.800s 1956.485us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.200s 9722.475us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 77.340s 8983.366us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 58.200s 4264.951us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2089.070s 381588.044us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.140s 19.478us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 27.527us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.390s 849.701us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.390s 849.701us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.480s 40.303us 5 5 100.00
kmac_csr_rw 1.430s 60.208us 20 20 100.00
kmac_csr_aliasing 7.030s 492.225us 5 5 100.00
kmac_same_csr_outstanding 3.060s 111.547us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.480s 40.303us 5 5 100.00
kmac_csr_rw 1.430s 60.208us 20 20 100.00
kmac_csr_aliasing 7.030s 492.225us 5 5 100.00
kmac_same_csr_outstanding 3.060s 111.547us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.740s 533.004us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.740s 533.004us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.740s 533.004us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.740s 533.004us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.430s 278.893us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 89.170s 27119.242us 5 5 100.00
kmac_tl_intg_err 5.290s 242.442us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.290s 242.442us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 58.200s 4264.951us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 65.670s 5904.052us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 391.150s 16575.775us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.740s 533.004us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 89.170s 27119.242us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 89.170s 27119.242us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 89.170s 27119.242us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 65.670s 5904.052us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 58.200s 4264.951us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 89.170s 27119.242us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 353.960s 15517.414us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 65.670s 5904.052us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 185.960s 24475.421us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 95194590967868831369576189813349346387334874220490742960444705073289916452460 75
UVM_FATAL @ 10036265594 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe5e99000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10036265594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 66690857187457191093592110101429868721928551544831221267227417383383071076689 75
UVM_FATAL @ 10030186382 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x844e0000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10030186382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 101319236649992657806924916905567635530493199226509481563876345133635945515235 75
UVM_FATAL @ 10037218551 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xad59a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10037218551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 108132081365838005429192453302187808057492976719415114111424007992583776401436 157
UVM_ERROR @ 2530896345 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2530896345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 113422452863759263343539732300193281820718183016130700027162685404690719220335 195
UVM_ERROR @ 12863136832 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12863136832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 39076836742556089585233831973952722795480909592262021293198235069586516875829 140
UVM_ERROR @ 4852067502 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4852067502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 51669715615798148997080330309059015479647237026873592837057439201943757987616 81
UVM_FATAL @ 10125498758 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x127d000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10125498758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 18536220667239823969323202285542959107302639644858460699976897400751879127434 82
UVM_FATAL @ 10052140639 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbd950000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10052140639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)
kmac_sideload_invalid 67430736238014573863287311740615644748241955600115380704382218685253286828610 90
UVM_FATAL @ 10283092509 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4b9f1000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10283092509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 72533555696055988697768653039783013430470116601662628944571412240341278668824 80
UVM_FATAL @ 10169609686 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x65632000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10169609686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 29367837483120013344447551928603193704037706893031651247461152116536310364349 81
UVM_FATAL @ 10140908740 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa7fc9000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10140908740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 114695541460664334024608201841598330266291499754835215465676293933415122741903 78
UVM_FATAL @ 10044309933 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4ca6b000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10044309933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 18144797240980533470750301280106599662281811676128201871885304677547783995519 95
UVM_FATAL @ 10116942849 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc9a0e000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10116942849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23)
kmac_sideload_invalid 100961945614529674353348875626031573508782338497219655487342394472449687927149 98
UVM_FATAL @ 10576277732 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8153b000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10576277732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 50068172156311605214641308339302113155648300870246838550824077226201681306387 92
UVM_FATAL @ 10669904637 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaa4c6000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10669904637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 12852870978220887373857824512725523026906513485751029213278468885310782241529 88
UVM_FATAL @ 10101597901 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1f0b2000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10101597901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---