Simulation Results: otbn

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 97.11 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 99.57 %
  • line
  • 99.67 %
  • branch
  • 95.02 %
  • toggle
  • 93.77 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.42%
V2S
99.09%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 140.665us 1 1 100.00
single_binary 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 5.000s 25.906us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 39.287us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 6.000s 232.908us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 51.726us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 64.557us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 39.287us 20 20 100.00
otbn_csr_aliasing 4.000s 51.726us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 47.000s 7114.044us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 17.000s 256.242us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 44.000s 159.434us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 52.000s 473.790us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 75.000s 214.503us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 93.000s 236.679us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 148.000s 624.471us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 10.000s 17.850us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 10.000s 41.683us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 7.000s 26.772us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 6.000s 43.304us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 7.000s 106.682us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 7.000s 106.682us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 5.000s 25.906us 5 5 100.00
otbn_csr_rw 8.000s 39.287us 20 20 100.00
otbn_csr_aliasing 4.000s 51.726us 5 5 100.00
otbn_same_csr_outstanding 5.000s 18.528us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 5.000s 25.906us 5 5 100.00
otbn_csr_rw 8.000s 39.287us 20 20 100.00
otbn_csr_aliasing 4.000s 51.726us 5 5 100.00
otbn_same_csr_outstanding 5.000s 18.528us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 43.170us 10 10 100.00
otbn_dmem_err 14.000s 159.069us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 11.000s 70.161us 5 5 100.00
otbn_controller_ispr_rdata_err 13.000s 68.954us 5 5 100.00
otbn_mac_bignum_acc_err 9.000s 90.336us 5 5 100.00
otbn_urnd_err 6.000s 17.656us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 10.000s 29.950us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 30.816us 2 2 100.00
otbn_non_sec_partial_wipe 6 10 60.00
otbn_partial_wipe 7.000s 28.539us 6 10 60.00
tl_intg_err 25 25 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
otbn_tl_intg_err 32.000s 264.257us 20 20 100.00
passthru_mem_tl_intg_err 16 20 80.00
otbn_passthru_mem_tl_intg_err 31.000s 172.549us 16 20 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 140.665us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 14.000s 159.069us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 43.170us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 32.000s 264.257us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 148.000s 624.471us 58 60 96.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 43.170us 10 10 100.00
otbn_dmem_err 14.000s 159.069us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.850us 5 5 100.00
otbn_illegal_mem_acc 10.000s 29.950us 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 43.170us 10 10 100.00
otbn_dmem_err 14.000s 159.069us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.850us 5 5 100.00
otbn_illegal_mem_acc 10.000s 29.950us 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 148.000s 624.471us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 13.000s 43.170us 10 10 100.00
otbn_dmem_err 14.000s 159.069us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.850us 5 5 100.00
otbn_illegal_mem_acc 10.000s 29.950us 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 8.000s 42.283us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 26.198us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 56.000s 182.634us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 56.000s 182.634us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 13.000s 41.209us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 12.000s 75.520us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 37.280us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 37.280us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 19.000s 74.561us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 75.000s 214.503us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 19.000s 40.168us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 31.000s 244.650us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 673.000s 2911.903us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 527.000s 2210.037us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 24919012610167833900709839357524635640480873438857847187105094672936699643752 241
UVM_ERROR @ 1006216927 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1006216927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 51381143215883858658467703713021755179899435695907766566582259900804800569889 224
UVM_ERROR @ 932070440 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 932070440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 24890595702029568475456899883433124723619646881855745093403073813029657772649 473
UVM_ERROR @ 656336367 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 656336367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 57647009430025415154013024309644110460159449408909307565611453606247598486381 175
UVM_ERROR @ 623433844 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 623433844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 39979218170080944177175835877869315864448144769431126208108563511148650047786 512
UVM_ERROR @ 2210037023 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2210037023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 114894505067266130047972046315252364662888562811998424895262482173457198873966 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 23019142 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 23019142 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 23019142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 88571618555821984761239796415477861197684791630551683757896643223384990207282 106
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 16214051 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 16214051 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 16214051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 30101700836882503489407315235300609679276482611015547886660440450578847889175 107
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 5105655 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 5105655 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 5105655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 95726394440810744570325382542861717015213816570102397147825671101317718873689 105
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3390605 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3390605 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3390605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 32796098770816354633238418707955097225951755108731018581607734691882571505287 164
UVM_FATAL @ 390298360 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 390298360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 45579534166339371629848053155712204718905312179407632438261565224191458032232 155
UVM_FATAL @ 48008276 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 48008276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_escalate 6949635853347414631783618267657130857001095367724060019863202362459400144446 112
UVM_FATAL @ 55624344 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 55624344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 14645600169108604407442580882256664907881787094190134092834138428988424588561 117
UVM_ERROR @ 6193736 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 6193736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 10791422167485281647427674433019378522908828436733110917357272669343668549250 83
UVM_FATAL @ 2770348 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 2770348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 46369027663082127809400522831195833373406870757002683044333971843022009057342 83
UVM_FATAL @ 12455048 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 12455048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 3181722978052095050277850315347308445683760842055515762867680980137398286712 93
UVM_FATAL @ 229853919 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 229853919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 37501535713664906353892231921747545183021393336758410316549009260160375195731 88
UVM_FATAL @ 10861221 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10861221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---