Simulation Results: pwm

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.73 %
  • code
  • 96.52 %
  • assert
  • 98.00 %
  • func
  • 98.68 %
  • block
  • 99.46 %
  • line
  • 99.58 %
  • branch
  • 99.10 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwm_smoke 5.000s 515.744us 10 10 100.00
csr_hw_reset 5 5 100.00
pwm_csr_hw_reset 2.000s 21.477us 5 5 100.00
csr_rw 20 20 100.00
pwm_csr_rw 2.000s 58.502us 20 20 100.00
csr_bit_bash 5 5 100.00
pwm_csr_bit_bash 8.000s 553.539us 5 5 100.00
csr_aliasing 5 5 100.00
pwm_csr_aliasing 3.000s 104.098us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
pwm_csr_mem_rw_with_rand_reset 2.000s 28.998us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
pwm_csr_rw 2.000s 58.502us 20 20 100.00
pwm_csr_aliasing 3.000s 104.098us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
pulse 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
blink 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
heartbeat 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
resolution 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
multi_channel 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
polarity 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
phase 50 50 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
pwm_phase 62.000s 10507.861us 25 25 100.00
lowpower 25 25 100.00
pwm_rand_output 76.000s 10718.291us 25 25 100.00
perf 10 10 100.00
pwm_perf 61.000s 10717.161us 10 10 100.00
regwen 1 1 100.00
pwm_regwen 350.000s 41976.062us 1 1 100.00
stress_all 25 25 100.00
pwm_stress_all 220.000s 55516.803us 25 25 100.00
alert_test 50 50 100.00
pwm_alert_test 2.000s 55.654us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
pwm_tl_errors 4.000s 137.727us 20 20 100.00
tl_d_illegal_access 20 20 100.00
pwm_tl_errors 4.000s 137.727us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
pwm_csr_hw_reset 2.000s 21.477us 5 5 100.00
pwm_csr_rw 2.000s 58.502us 20 20 100.00
pwm_csr_aliasing 3.000s 104.098us 5 5 100.00
pwm_same_csr_outstanding 3.000s 245.708us 20 20 100.00
tl_d_partial_access 50 50 100.00
pwm_csr_hw_reset 2.000s 21.477us 5 5 100.00
pwm_csr_rw 2.000s 58.502us 20 20 100.00
pwm_csr_aliasing 3.000s 104.098us 5 5 100.00
pwm_same_csr_outstanding 3.000s 245.708us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
pwm_sec_cm 2.000s 186.294us 5 5 100.00
pwm_tl_intg_err 3.000s 86.270us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
pwm_tl_intg_err 3.000s 86.270us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 10 10 100.00
pwm_heartbeat_wrap 68.000s 174982.976us 10 10 100.00

Error Messages

   Test seed line log context