rom_ctrl Simulation Results

Simulation Results: rom_ctrl

25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	8.930s	1964.792us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	9.560s	554.816us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	6.200s	168.934us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	5.350s	1806.443us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	5.210s	193.989us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	6.740s	159.656us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	6.200s	168.934us	20	20	100.00
	rom_ctrl_csr_aliasing	5.210s	193.989us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	5.340s	816.935us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	7.070s	9892.932us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.090s	960.315us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	26.950s	588.731us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	9.380s	558.080us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	8.460s	548.862us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	10.450s	604.176us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	10.450s	604.176us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.560s	554.816us	5	5	100.00
	rom_ctrl_csr_rw	6.200s	168.934us	20	20	100.00
	rom_ctrl_csr_aliasing	5.210s	193.989us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.160s	133.770us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.560s	554.816us	5	5	100.00
	rom_ctrl_csr_rw	6.200s	168.934us	20	20	100.00
	rom_ctrl_csr_aliasing	5.210s	193.989us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.160s	133.770us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	37.580s	12515.104us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00
	rom_ctrl_tl_intg_err	70.120s	845.357us	20	20	100.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	8.930s	1964.792us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	8.930s	1964.792us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	8.930s	1964.792us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	70.120s	845.357us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
	rom_ctrl_kmac_err_chk	9.380s	558.080us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	120.960s	18696.238us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	37.580s	12515.104us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	288.720s	577.381us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	574.500s	22046.396us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	43279742585281070038949541667770918817570800616917774425727053648147246627663	165	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 5883089ps failed at 5883089ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 5883089ps failed at 5883089ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	17820717571335339029398309059468360337531506652102974530153432057946220047895	107	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 5015700ps failed at 5015700ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 5025700ps failed at 5025700ps Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	81646276451702459716450593304248461229799830952183688791239449213286570035349	238	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13359215ps failed at 13359215ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13370326ps failed at 13370326ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	44585355032376237781876424397402165401820462600611641622882612849164384669055	114	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 15835898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 15835898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 15835898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))