Simulation Results: rom_ctrl

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.45%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 13.870s 4019.517us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 15.730s 296.811us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 16.080s 1049.966us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 14.650s 3970.493us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 10.080s 335.112us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.850s 1171.554us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 16.080s 1049.966us 20 20 100.00
rom_ctrl_csr_aliasing 10.080s 335.112us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 10.610s 289.077us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 12.250s 301.129us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 14.920s 3713.379us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 50.870s 1061.965us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 17.110s 2104.534us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 12.540s 5526.302us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 14.190s 540.128us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 14.190s 540.128us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 15.730s 296.811us 5 5 100.00
rom_ctrl_csr_rw 16.080s 1049.966us 20 20 100.00
rom_ctrl_csr_aliasing 10.080s 335.112us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.000s 1067.389us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 15.730s 296.811us 5 5 100.00
rom_ctrl_csr_rw 16.080s 1049.966us 20 20 100.00
rom_ctrl_csr_aliasing 10.080s 335.112us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.000s 1067.389us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 73.780s 6446.022us 20 20 100.00
tl_intg_err 21 25 84.00
rom_ctrl_tl_intg_err 126.330s 1489.300us 20 20 100.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
prim_fsm_check 1 5 20.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
prim_count_check 1 5 20.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_compare_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 13.870s 4019.517us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 13.870s 4019.517us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 13.870s 4019.517us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 126.330s 1489.300us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
rom_ctrl_kmac_err_chk 17.110s 2104.534us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 221.290s 22305.020us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 73.780s 6446.022us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 559.740s 2397.414us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 344.080s 5393.862us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 77480434147660868169950479824854083015719109965401717755865524300979826084912 421
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 97966966ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 97966966ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 97966966ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
rom_ctrl_sec_cm 114843118331588254423307870087929278338013228171828467520186026229325143009797 180
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 48830789ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 48830789ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 48830789ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 97242011271294691851689699539248985391281638184917172188014767358999771476334 301
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 102554634ps failed at 102554634ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 102554634ps failed at 102554634ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 103685258621133945892942770165883895952538917652763275178830998226938262930564 109
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 11903004ps failed at 11903004ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11903004ps failed at 11903004ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'