Simulation Results: rstmgr

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.520s 187.457us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 0.840s 128.040us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 6.990s 2009.843us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.520s 154.916us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.460s 195.776us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00
rstmgr_csr_aliasing 1.520s 154.916us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.190s 202.624us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.740s 527.866us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.370s 227.193us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.330s 1936.347us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.330s 1936.347us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.330s 1936.347us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.330s 1936.347us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 59.440s 25428.866us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.030s 80.490us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.560s 568.406us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.560s 568.406us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 0.840s 128.040us 5 5 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00
rstmgr_csr_aliasing 1.520s 154.916us 5 5 100.00
rstmgr_same_csr_outstanding 1.300s 219.747us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 0.840s 128.040us 5 5 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00
rstmgr_csr_aliasing 1.520s 154.916us 5 5 100.00
rstmgr_same_csr_outstanding 1.300s 219.747us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 27.170s 16804.116us 5 5 100.00
rstmgr_tl_intg_err 2.560s 922.421us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 27.170s 16804.116us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 27.170s 16804.116us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 2.560s 922.421us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.470s 164.165us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.190s 2445.504us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.300s 301.164us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 27.170s 16804.116us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.820s 62.152us 20 20 100.00

Error Messages

   Test seed line log context