rstmgr_cnsty_chk Simulation Results

Simulation Results: rstmgr_cnsty_chk

25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

90.00%

unmapped

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				9	10	90.00
	rstmgr_cnsty_chk_test	3.380s	10769.663us	9	10	90.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	25629969752154841089046258135141413863029016291931558675498319619852347088066	172	UVM_ERROR @ 1766491203 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1784251203 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1802011203 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1819771203 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1837531203 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16