| V1 |
|
100.00% |
| V2 |
|
94.38% |
| V2S |
|
100.00% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.800s | 892.708us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.760s | 13.244us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.850s | 13.997us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.910s | 2402.770us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.990s | 38.848us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.350s | 60.001us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.850s | 13.997us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.990s | 38.848us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 6.850s | 11890.585us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.760s | 2965.820us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 448.800s | 357165.408us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 448.800s | 357165.408us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 7.830s | 4738.852us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 14.763us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.890s | 30.691us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.280s | 344.013us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.280s | 344.013us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.760s | 13.244us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.850s | 13.997us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.990s | 38.848us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 66.319us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.760s | 13.244us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.850s | 13.997us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.990s | 38.848us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 66.319us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.260s | 393.057us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.610s | 114.701us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.610s | 114.701us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 3 | 10 | 30.00 | |||
| rv_timer_min | 1.620s | 2038.964us | 3 | 10 | 30.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 2.030s | 43.973us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 12 | 20 | 60.00 | |||
| rv_timer_stress_all_with_rand_reset | 40.230s | 45307.590us | 12 | 20 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 37120599521528443242031736178748928886217675272251789604684335240474547481597 | 72 |
UVM_FATAL @ 213974250 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x98a82304) == 0x1
UVM_INFO @ 213974250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42116929433658992410849797521011961624251304192382265303872746275068551087138 | 72 |
UVM_FATAL @ 1078984551 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x780a9304) == 0x1
UVM_INFO @ 1078984551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 17269614305924017881239265179382450148188404543630276100168394859145903775876 | 72 |
UVM_FATAL @ 66061548 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x45c50d04) == 0x1
UVM_INFO @ 66061548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 48829707790166114385470148236070630582923900605778464699236149873283105421206 | 72 |
UVM_FATAL @ 83134128 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xaedd2504) == 0x1
UVM_INFO @ 83134128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28962143872155554934407766937436613339791187029945192127507996104702402470060 | 72 |
UVM_FATAL @ 98372998 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x65c44504) == 0x1
UVM_INFO @ 98372998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 69396957039756756910398513373224293751815375753492997914999700590535986972210 | 72 |
UVM_FATAL @ 114913710 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6b6de504) == 0x1
UVM_INFO @ 114913710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 102284137143214789382415724002586303276308403195040967385216490859881384400209 | 73 |
UVM_FATAL @ 71929627 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd2df5104) == 0x1
UVM_INFO @ 71929627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 77478512770963267437091992395150575823995861071906890626397501144422453949162 | 72 |
UVM_FATAL @ 60926399 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x62290504) == 0x1
UVM_INFO @ 60926399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 97221742573115878439795009621387207679639287678606971367851846953185517716511 | 73 |
UVM_FATAL @ 11890585345 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x254b5f04) == 0x1
UVM_INFO @ 11890585345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 101310837474001269159033804100773628676500779850126831857147265674761333857141 | 72 |
UVM_FATAL @ 58333153 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x51e37504) == 0x1
UVM_INFO @ 58333153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 1786890399994033770272702132376542426233419059722145342687616348490083919587 | 72 |
UVM_FATAL @ 2074557132 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa1a9e104) == 0x1
UVM_INFO @ 2074557132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 95588836949782413576810158689320581625520828822076325195441777865964201025852 | 73 |
UVM_FATAL @ 488413770 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa8630904) == 0x1
UVM_INFO @ 488413770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 37634509787073181614946168507869211955713207405722345131795204374387304807586 | 72 |
UVM_FATAL @ 113510725 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xae6f5304) == 0x1
UVM_INFO @ 113510725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 36715571377896564555666015252401999931664357575840616924192261429911063986128 | 72 |
UVM_FATAL @ 2038964154 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf4913504) == 0x1
UVM_INFO @ 2038964154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 1559417849918694319057460986146503676724278557813986433686919290274581763683 | 72 |
UVM_FATAL @ 65791916 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x61eb1704) == 0x1
UVM_INFO @ 65791916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96482285410293791390190775914906525420302059636907532215617081849480585698326 | 72 |
UVM_FATAL @ 54372940 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x789c2904) == 0x1
UVM_INFO @ 54372940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 49673665090407025949959534516067202303817482834868504955380547086276415451880 | 72 |
UVM_FATAL @ 1039603343 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb3f87704) == 0x1
UVM_INFO @ 1039603343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 60980022112173945809289105787006693840044433610796566979501620689631141107551 | 72 |
UVM_FATAL @ 396410329 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbb529b04) == 0x1
UVM_INFO @ 396410329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44287454710316288826235672021844865755740057651014702725826805721981678351059 | 72 |
UVM_FATAL @ 1075843187 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb0aa7b04) == 0x1
UVM_INFO @ 1075843187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 9092318112979657818824841829824437496375950899074804399103638444547491304 | 72 |
UVM_FATAL @ 3038505826 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x40cf0904) == 0x1
UVM_INFO @ 3038505826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 52870775991808871150011496208826305732331867323565504420195377995430965739075 | 72 |
UVM_FATAL @ 128656188 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x22005104) == 0x1
UVM_INFO @ 128656188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 94875392742250534825045027892145519848546649317823308430169966135485339496359 | 72 |
UVM_FATAL @ 133011375 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf658f904) == 0x1
UVM_INFO @ 133011375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 23479748514146965660963675914708583551770467179509788622092021120737572696311 | 73 |
UVM_FATAL @ 212859674 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7aa4c504) == 0x1
UVM_INFO @ 212859674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 113857211971184250433625451621300985016212747161655626441947593991775103833212 | 72 |
UVM_FATAL @ 83002719 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7f641704) == 0x1
UVM_INFO @ 83002719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35820903872871935341888046326342626155475387876840810035110621462691910013883 | 72 |
UVM_FATAL @ 81954920 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfd807d04) == 0x1
UVM_INFO @ 81954920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 93987389893324145050856934320579491912931561231458912885161244743904208908882 | 72 |
UVM_ERROR @ 170212707 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170212707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 93367719730021002295587061701940705482943520562599413717592324620293535876837 | 72 |
UVM_ERROR @ 43252766 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43252766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 36653760898596603783652251750334164741654030405536875059573632984101467435364 | 72 |
UVM_ERROR @ 170552195 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170552195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 61592167763740500685634687782540450780731720613152154303029754942639709407986 | 72 |
UVM_ERROR @ 177143552 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 177143552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 72148421684418389403347168109214589856377670791275757260348777136036316180209 | 72 |
UVM_ERROR @ 321371500 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 321371500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112208895102526444011595831742651912726292077524742038238281937775456504715524 | 73 |
UVM_ERROR @ 179005213 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 179005213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 55310582392620573198255331217635746746292453152607330954174686463815075024776 | 72 |
UVM_ERROR @ 43972836 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43972836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 12655863190740845323025139455108204030164602242829309072742843804320675298286 | 72 |
UVM_ERROR @ 168154271 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 168154271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 66562061299948703568214393358427820585858534389274948321601793149598740587963 | 108 |
UVM_FATAL @ 1710312770 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1710312770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 11305149233927405173944543026473880062902560208081188043869738307554758943026 | 104 |
UVM_FATAL @ 75304750 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 75304750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | ||||
| rv_timer_max | 46604960543628401462835559066877424391486699349604489697125941211015056955727 | 72 |
UVM_ERROR @ 42743648 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 42743648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 53893062940093995693068535037988832926857354360799002566411578384272888313530 | 384 |
UVM_ERROR @ 2474692646 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2474692646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 80616535710092760292015162734135515204852813790000432847411912974457865502124 | 167 |
UVM_ERROR @ 1931150339 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1931150339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 19548341320488538977574643505623518408679364034324659598803815474230970868319 | 280 |
UVM_ERROR @ 1161647986 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1161647986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 7490144191013046761178440505850188589773150010648484221925527031784807965397 | 297 |
UVM_ERROR @ 4547767576 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4547767576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 45492310754930724458452070131418506059708392500775769775864188074176408282580 | 238 |
UVM_ERROR @ 4462639657 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4462639657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| rv_timer_stress_all_with_rand_reset | 5757340777877223925444179006535106568873900301780205091574808459771381982104 | 112 |
UVM_ERROR @ 1069032260 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1069032260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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