Simulation Results: spi_device

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 94.28 %
  • assert
  • 94.41 %
  • func
  • 99.21 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.91%
V2S
100.00%
unmapped
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 355.750s 75492.942us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.630s 40.414us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 3.120s 637.834us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 31.950s 3551.332us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 19.290s 1032.568us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 4.070s 1298.449us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 3.120s 637.834us 20 20 100.00
spi_device_csr_aliasing 19.290s 1032.568us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.070s 11.961us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.530s 57.007us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.190s 55.666us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.460s 17.368us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.710s 78.115us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 10.220s 963.116us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 10.220s 963.116us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 18.720s 42716.825us 50 50 100.00
spi_device_tpm_sts_read 1.390s 156.210us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 45.250s 9366.540us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 33.440s 9359.833us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 30.620s 13458.464us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 30.620s 13458.464us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 21.900s 2629.635us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 21.900s 2629.635us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 21.900s 2629.635us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 21.900s 2629.635us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 21.900s 2629.635us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 24.490s 8662.853us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 123.070s 16876.715us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 123.070s 16876.715us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 123.070s 16876.715us 50 50 100.00
cmd_read_buffer 98 100 98.00
spi_device_flash_mode 38.530s 6028.809us 48 50 96.00
spi_device_read_buffer_direct 14.680s 2668.219us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 123.070s 16876.715us 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 197.490s 23782.678us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 17.590s 5267.115us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 17.590s 5267.115us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 355.750s 75492.942us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 375.180s 247205.111us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 921.620s 113484.459us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.130s 15.400us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.200s 44.376us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 5.410s 226.916us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 5.410s 226.916us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.630s 40.414us 5 5 100.00
spi_device_csr_rw 3.120s 637.834us 20 20 100.00
spi_device_csr_aliasing 19.290s 1032.568us 5 5 100.00
spi_device_same_csr_outstanding 4.650s 318.619us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.630s 40.414us 5 5 100.00
spi_device_csr_rw 3.120s 637.834us 20 20 100.00
spi_device_csr_aliasing 19.290s 1032.568us 5 5 100.00
spi_device_same_csr_outstanding 4.650s 318.619us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_sec_cm 1.550s 65.844us 5 5 100.00
spi_device_tl_intg_err 18.820s 6109.097us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 18.820s 6109.097us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 49 50 98.00
spi_device_flash_mode_ignore_cmds 405.180s 333005.963us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*])
spi_device_flash_mode 21768408385761057307805571081536517565807102481196533812294870356096619355597 73
UVM_ERROR @ 3287818798 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3287818798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_device_flash_mode_ignore_cmds 54335346160822293481014718317613895330294434857456095146088421051209553072238 123
UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_mode 67403937512450519556438571219540484670378642965467260264334656060685105090756 73
UVM_ERROR @ 142930252 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10130432 [0x9a9400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x9a9400 != exp 0x0
UVM_INFO @ 1040170252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---