Simulation Results: spi_host

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 97.000s 10135.812us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 104.295us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 42.043us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 3.000s 249.968us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 45.448us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 36.632us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 42.043us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.448us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 15.441us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 31.685us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 3.000s 161.579us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 87.000s 9222.407us 50 50 100.00
spi_host_error_cmd 2.000s 61.116us 50 50 100.00
spi_host_event 292.000s 21698.955us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 916.726us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 916.726us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 916.726us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 250.000s 9440.856us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 23.392us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 916.726us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 916.726us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 97.000s 10135.812us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 97.000s 10135.812us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 64.000s 12381.904us 50 50 100.00
spien 50 50 100.00
spi_host_spien 178.000s 16721.436us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 695.000s 21607.676us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 15.000s 3679.862us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 87.000s 9222.407us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 15.649us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 35.563us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 535.608us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 535.608us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 104.295us 5 5 100.00
spi_host_csr_rw 2.000s 42.043us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.448us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 18.881us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 104.295us 5 5 100.00
spi_host_csr_rw 2.000s 42.043us 20 20 100.00
spi_host_csr_aliasing 2.000s 45.448us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 18.881us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 77.202us 5 5 100.00
spi_host_tl_intg_err 3.000s 477.589us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 477.589us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 410.000s 22245.055us 10 10 100.00

Error Messages

   Test seed line log context