Simulation Results: sram_ctrl

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.95%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 117.460s 1383.109us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.080s 53.733us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.050s 50.482us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.460s 181.933us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.060s 19.813us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.010s 362.583us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.050s 50.482us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 19.813us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 343.710s 13813.675us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 192.960s 20407.265us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1107.920s 10012.447us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 386.410s 5709.322us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2354.550s 689719.994us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1283.500s 14245.603us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 118.960s 56849.010us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1327.460s 551712.067us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 106.050s 1994.839us 50 50 100.00
sram_ctrl_partial_access_b2b 549.390s 85564.079us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 107.630s 803.294us 50 50 100.00
sram_ctrl_throughput_w_partial_write 105.200s 1584.441us 50 50 100.00
sram_ctrl_throughput_w_readback 107.480s 1950.950us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1446.770s 17534.847us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.400s 2104.121us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 6025.680s 560913.333us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.060s 15.803us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.020s 275.132us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.020s 275.132us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 53.733us 5 5 100.00
sram_ctrl_csr_rw 1.050s 50.482us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 19.813us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 26.201us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 53.733us 5 5 100.00
sram_ctrl_csr_rw 1.050s 50.482us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 19.813us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 26.201us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.930s 7483.558us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
sram_ctrl_tl_intg_err 3.420s 479.777us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.420s 479.777us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1446.770s 17534.847us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1446.770s 17534.847us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.050s 50.482us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1327.460s 551712.067us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1327.460s 551712.067us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1327.460s 551712.067us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 118.960s 56849.010us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 37 50 74.00
sram_ctrl_mubi_enc_err 8.670s 2884.306us 37 50 74.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.930s 7483.558us 20 20 100.00
sec_cm_mem_readback 38 50 76.00
sram_ctrl_readback_err 9.850s 4390.012us 38 50 76.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 117.460s 1383.109us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 117.460s 1383.109us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1327.460s 551712.067us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 118.960s 56849.010us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 117.460s 1383.109us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.980s 2.857us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 268.220s 57673.945us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 102359310904546634757966086251250362922005677288101159010236773294527278861724 95
UVM_ERROR @ 1377277728 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x77) != exp (0x6c)
UVM_INFO @ 1377277728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 15946436209224260620080913045949903513297728587154939814049245715167954480555 95
UVM_ERROR @ 685852671 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x70)
UVM_INFO @ 685852671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 105455882879743479083461411112011699287988921542943049415201642827556184985818 95
UVM_ERROR @ 2744689937 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x17)
UVM_INFO @ 2744689937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 67010989110262802473770859520713276950793344178977138887028231583859943649706 95
UVM_ERROR @ 1372845508 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x75)
UVM_INFO @ 1372845508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 11991522399420548714128012428230907941334821980555679105730896037638213382859 95
UVM_ERROR @ 867332038 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x4a)
UVM_INFO @ 867332038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 82111017094292272221635098898396390912218644182331667942956795886211875024329 95
UVM_ERROR @ 4849783390 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x78)
UVM_INFO @ 4849783390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 92141996220760493521208704569900169197383779549299025256717010622901243271733 95
UVM_ERROR @ 668486445 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x1d)
UVM_INFO @ 668486445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 4702925140146394545363056088946570694678226960951777758138977506990017194079 95
UVM_ERROR @ 672588225 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x30)
UVM_INFO @ 672588225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 112299967457714671692352731976842777196270623548111830406675125079462508807338 95
UVM_ERROR @ 731217195 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x2a)
UVM_INFO @ 731217195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 40754438340225476195393153588940686010271968318007200293508191175138690386455 95
UVM_ERROR @ 708477508 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x61)
UVM_INFO @ 708477508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 67167876901971764558677406627808104959362637204381303949278062798866807309307 95
UVM_ERROR @ 657829709 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x34) != exp (0x1c)
UVM_INFO @ 657829709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 98886761752299120829285459663297563774787831935730678172369640923461515094444 95
UVM_ERROR @ 1688984337 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x52) != exp (0x15)
UVM_INFO @ 1688984337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 76261107206505140058404479799686217181118809587686801848626931991579336376228 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 8310831009 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 8310831009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 113807867347728997969233639022140334001260204790950377156147092236721708277588 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 666907503 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 666907503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 50767208187264240630411644286286906737200486420047338018231281204069008006636 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1342111563 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1342111563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 6318960745551430999844998825513933493246532445555280824097839854118475767283 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2648078745 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2648078745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 69841571712520027433006626588290851873570828212224979107216230153665559792215 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1373813787 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1373813787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 27501902807525182933167925707524960726436907608076359860850727712139078064243 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 675334404 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 675334404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 33735718123979609939386594440308236895357000787046479738880978775951022998620 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 695400423 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 695400423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 21874083065515904409620908246804716247160861403364099123055063587789659975804 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 709057419 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 709057419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 42220015258265465976877141654202607170552595385967394746666941273620295291282 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2649945854 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2649945854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 8182110815156175342855840402554290552244706535771154011806856351102973515501 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2745838460 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2745838460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 81243659423483385274458378018460166728567805305541300387897383060853470876847 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 9378705188 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 9378705188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 102687403564740528782877510298409607460069855726741234736226070222635447006159 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 692487317 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 692487317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 36517962182940515878300369698440909334389780906329016236354877767579769316582 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2884305663 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2884305663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 101097609567459174018059267109803321340616763880451138695983359282908062747299 96
UVM_ERROR @ 2856796 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2856796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 48126024284666193268359228664953611319389958397055145956071095785919132254374 97
UVM_ERROR @ 3703461 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3703461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 47673515144829421715128799707017721234597167774986310156331485191628447597536 98
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 1480675 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1480675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 51911804351169007382814922942513601913370485141508129109897280918275591617150 97
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1065268ps failed at 1065268ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1075268ps failed at 1075268ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 108365656413500165950809175757517725686012035036055419365747352276244196741556 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 4064247 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 4064247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---