Simulation Results: sram_ctrl

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.13%
V2
100.00%
V2S
94.10%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 106.880s 730.016us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.030s 162.675us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.000s 38.393us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.070s 742.891us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.040s 15.110us 5 5 100.00
csr_mem_rw_with_rand_reset 18 20 90.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.920s 162.175us 18 20 90.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.000s 38.393us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 15.110us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 13.440s 9305.870us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 6.890s 781.872us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1733.650s 19897.870us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 350.090s 33322.294us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 76.890s 10421.951us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1618.940s 5439.145us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 10.660s 3452.759us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1670.230s 15809.707us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 100.070s 7007.933us 50 50 100.00
sram_ctrl_partial_access_b2b 563.550s 47250.179us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 99.910s 269.542us 50 50 100.00
sram_ctrl_throughput_w_partial_write 101.500s 166.835us 50 50 100.00
sram_ctrl_throughput_w_readback 105.560s 5599.828us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1277.640s 52410.202us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.200s 32.004us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 3758.650s 196498.733us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.020s 37.540us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.690s 166.077us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.690s 166.077us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 162.675us 5 5 100.00
sram_ctrl_csr_rw 1.000s 38.393us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 15.110us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 50.127us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.030s 162.675us 5 5 100.00
sram_ctrl_csr_rw 1.000s 38.393us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 15.110us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 50.127us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.980s 2256.523us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
sram_ctrl_tl_intg_err 3.510s 1080.353us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.510s 1080.353us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1277.640s 52410.202us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1277.640s 52410.202us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.000s 38.393us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1670.230s 15809.707us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1670.230s 15809.707us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1670.230s 15809.707us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 10.660s 3452.759us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 1.580s 156.800us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.980s 2256.523us 20 20 100.00
sec_cm_mem_readback 42 50 84.00
sram_ctrl_readback_err 1.680s 149.744us 42 50 84.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 106.880s 730.016us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 106.880s 730.016us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1670.230s 15809.707us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 10.660s 3452.759us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 106.880s 730.016us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.940s 7.347us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
sram_ctrl_stress_all_with_rand_reset 993.760s 2912.350us 49 50 98.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 15062449666182716373173513300421555749733158970887783971246751756641345241832 97
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3701562ps failed at 3701562ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 7241562 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7241562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
sram_ctrl_sec_cm 51496508308000564643698771341961420430146346188252519661067027420433227837077 98
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4126620ps failed at 4126620ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 7346620 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7346620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 110289730656937281129507975459698877114082147957716319139418102178271817552036 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 3925924 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 3925924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 85611554221273891500546368990533566926157226035396315619859152333683781229574 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3708505 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3708505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 102176963472652671453447263375974656485619381803569795773107419808976455411586 97
UVM_ERROR @ 4585536 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4585536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 13659986701911898493430047498207883979230663656877490147967506628503252135789 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 137514442 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 137514442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 104353288872419636212826713948390135111579568246868608068809386483189402880233 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 33356250 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 33356250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 79424751938311231359742660429790806879757271974085408044812740552376671478111 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 130173965 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 130173965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 26663359041150584568464556855619661894864942468978816921863830761679821653734 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 293092642 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 293092642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 78683719240721708184059257650992920587478692379946818470813358346230227765756 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 100039721 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 100039721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 43792602370787404812492832833114306471734551819747880165536982144277966993730 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 49490393 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 49490393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 3525595055214362268528399696333454588342500376281056633225092792580095868956 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 29236914 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 29236914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 17265135331448936988501245773272776591411876779678843946291721465183957318236 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 27098340 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 27098340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 37082342396147818815296733732641384030453056268236415765726102451780635411127 95
UVM_ERROR @ 102252621 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x37)
UVM_INFO @ 102252621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 1896365752522391542567882718442024365258126565759188396754003446926678803500 95
UVM_ERROR @ 24961133 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x57)
UVM_INFO @ 24961133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12707632872781376627275648526416140171637338041808074067173427848637968456188 95
UVM_ERROR @ 45951227 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x58)
UVM_INFO @ 45951227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 77615143460046877736530428150686928025235781746108822322554462447768799656498 95
UVM_ERROR @ 27885766 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x5f)
UVM_INFO @ 27885766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 35720697152308321487652275339873909489684498290569423328331366355984930924884 95
UVM_ERROR @ 112557216 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x4c)
UVM_INFO @ 112557216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 6272322805861291107801952432054084331774763317810281693111183199684926042022 95
UVM_ERROR @ 52802433 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x77)
UVM_INFO @ 52802433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 107574073787830379283403862918585187210729556500465627218790783482677289372079 95
UVM_ERROR @ 71693584 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x44) != exp (0x3a)
UVM_INFO @ 71693584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 33520613255007697029414342675350109354357443749331687941144040665639090236903 95
UVM_ERROR @ 89665137 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x78) != exp (0x56)
UVM_INFO @ 89665137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 87128295041883162478752384932539317063521265761022391206978614432985643754140 101
UVM_ERROR @ 3392453546 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3392453546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 44985935813992492168791855951949543348528401494608705322007295739204328480607 95
UVM_ERROR @ 46000624 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 46000624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 22959791488527182376101266104246208926726818151031751785847538515397067786336 101
UVM_ERROR @ 237704818 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 237704818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---