Simulation Results: sysrst_ctrl

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.78 %
  • code
  • 98.34 %
  • assert
  • 98.37 %
  • func
  • 81.64 %
  • line
  • 99.01 %
  • branch
  • 99.15 %
  • cond
  • 98.04 %
  • toggle
  • 100.00 %
  • FSM
  • 95.51 %
Validation stages
V1
100.00%
V2
98.11%
V2S
100.00%
V3
94.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sysrst_ctrl_smoke 8.860s 2108.017us 50 50 100.00
input_output_inverted 50 50 100.00
sysrst_ctrl_in_out_inverted 10.220s 2444.296us 50 50 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 8.980s 2431.706us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 9.170s 2267.615us 5 5 100.00
csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_hw_reset 11.000s 6057.242us 5 5 100.00
csr_rw 20 20 100.00
sysrst_ctrl_csr_rw 8.480s 2053.300us 20 20 100.00
csr_bit_bash 5 5 100.00
sysrst_ctrl_csr_bit_bash 28.070s 74313.522us 5 5 100.00
csr_aliasing 5 5 100.00
sysrst_ctrl_csr_aliasing 15.640s 3125.586us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 9.150s 2044.006us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sysrst_ctrl_csr_rw 8.480s 2053.300us 20 20 100.00
sysrst_ctrl_csr_aliasing 15.640s 3125.586us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 50 50 100.00
sysrst_ctrl_combo_detect 381.030s 147197.530us 50 50 100.00
combo_detect_with_pre_cond 92 100 92.00
sysrst_ctrl_combo_detect_with_pre_cond 336.400s 146705.931us 92 100 92.00
auto_block_key_outputs 50 50 100.00
sysrst_ctrl_auto_blk_key_output 686.020s 287715.794us 50 50 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 2624.340s 1189838.708us 50 50 100.00
pin_output_keyboard_inversion_control 50 50 100.00
sysrst_ctrl_pin_override_test 11.250s 2510.078us 50 50 100.00
pin_input_value_accessibility 50 50 100.00
sysrst_ctrl_pin_access_test 9.020s 2225.010us 50 50 100.00
ec_power_on_reset 50 50 100.00
sysrst_ctrl_ec_pwr_on_rst 2326.870s 1026937.232us 50 50 100.00
flash_write_protect_output 50 50 100.00
sysrst_ctrl_flash_wr_prot_out 10.760s 2609.123us 50 50 100.00
ultra_low_power_test 46 50 92.00
sysrst_ctrl_ultra_low_pwr 28.070s 595024.767us 46 50 92.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 39.130s 35335.901us 2 2 100.00
stress_all 47 50 94.00
sysrst_ctrl_stress_all 436.580s 186614.776us 47 50 94.00
alert_test 50 50 100.00
sysrst_ctrl_alert_test 8.460s 2015.179us 50 50 100.00
intr_test 50 50 100.00
sysrst_ctrl_intr_test 8.370s 2016.255us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sysrst_ctrl_tl_errors 9.860s 2035.831us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sysrst_ctrl_tl_errors 9.860s 2035.831us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 11.000s 6057.242us 5 5 100.00
sysrst_ctrl_csr_rw 8.480s 2053.300us 20 20 100.00
sysrst_ctrl_csr_aliasing 15.640s 3125.586us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 31.480s 9504.829us 20 20 100.00
tl_d_partial_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 11.000s 6057.242us 5 5 100.00
sysrst_ctrl_csr_rw 8.480s 2053.300us 20 20 100.00
sysrst_ctrl_csr_aliasing 15.640s 3125.586us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 31.480s 9504.829us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
sysrst_ctrl_sec_cm 116.360s 42013.068us 5 5 100.00
sysrst_ctrl_tl_intg_err 75.840s 22252.222us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
sysrst_ctrl_tl_intg_err 75.840s 22252.222us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 47 50 94.00
sysrst_ctrl_stress_all_with_rand_reset 47.000s 1496943.707us 47 50 94.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 111324723031428009478793754599473332603777323370527286472195107284729615929092 659
UVM_ERROR @ 13381285747 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 13381285747 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13381285747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 61486681643652404219426548837238240080907122450360356298586314664034546477140 684
UVM_ERROR @ 37128310944 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 37128310944 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37128310944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 83645526854956235225712427702062473823386469012760428971674442515174646372194 700
UVM_ERROR @ 86381528120 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 86381528120 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 86381528120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 18779359354155623796758052583290441792774257546051774462258442225648686591318 758
UVM_ERROR @ 137058451602 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 137058451602 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 137058451602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 13380839533876921969455102993932306874468106164333776417537533743954297659044 746
UVM_ERROR @ 117677958597 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 117677958597 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 117677958597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 26031338448887380451929106581545146063816378707734154986137882863743080501511 709
UVM_ERROR @ 63237339569 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 63237339569 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 63237339569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
sysrst_ctrl_ultra_low_pwr 53417383028228766425610095329597908438004289853151974347271326056918263923018 647
UVM_ERROR @ 2322181434 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
UVM_INFO @ 2494681434 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 7814681434 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 10304740522 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 10314100522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
sysrst_ctrl_stress_all 114400741272815285216659948779463208727489972822439398526067997887189955081075 666
UVM_ERROR @ 11597089217 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
UVM_INFO @ 11774589217 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 13009840598 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 13058000598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 109675917321735075662904976245946039308662131918265547835489186883447408727525 650
UVM_ERROR @ 9825794442 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 9825828924 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 9825828924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all 19995754745194151568754171316827013787590309554182342808703021086814740018009 656
UVM_ERROR @ 263243169439 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 263243205803 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 263243205803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 6133411414986571081430574658183781553635948425676049252621950392833120471226 647
UVM_ERROR @ 3282906372 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3282989706 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3282989706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all 84592157089419381628730308286552645852965180947172910253037464982355365422591 658
UVM_ERROR @ 7355067779 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 7355087779 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 7355087779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 95830091126490943040226828527886767873383005421778063822357882289075604613472 648
UVM_ERROR @ 4274259830 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4274482052 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4274482052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*])
sysrst_ctrl_stress_all_with_rand_reset 72997748472775724825197134838855068190096297104932900182653611121779792803178 712
UVM_ERROR @ 17847693379 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 17847693379 ps: (sysrst_ctrl_pin_access_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key2_in == rdata_key2_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 17847693379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*
sysrst_ctrl_combo_detect_with_pre_cond 15177746598976129523595678418169185667361516730100666314419647159784008905187 690
UVM_ERROR @ 26003326015 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 36164174683 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19
UVM_INFO @ 36164214683 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2d
UVM_INFO @ 38208326015 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 38208494683 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:36) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (* [*] vs * [*])
sysrst_ctrl_stress_all_with_rand_reset 97655382476391999555897751570109424268801254189559810248505466727934154409406 673
UVM_ERROR @ 4694998367 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 4694998367 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4694998367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*])
sysrst_ctrl_stress_all_with_rand_reset 104415480121592309880771516051426013141069063951823798050285833640147802944514 659
UVM_ERROR @ 4085012799 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 4085012799 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4085012799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o
sysrst_ctrl_combo_detect_with_pre_cond 76915640800324177473921949930903731524615600847281776077624354255236978263247 664
UVM_ERROR @ 13386458346 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
UVM_INFO @ 13446458346 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0
UVM_INFO @ 13446458346 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :3
UVM_INFO @ 13621458346 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13641458346 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0