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---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"3.adc_ctrl_clock_gating.100913747707670421376885500060982623192027186868008044944097117158238730406270","seed":100913747707670421376885500060982623192027186868008044944097117158238730406270,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"24.adc_ctrl_clock_gating.32575952544210805816121717540196866756760803562104302401499460783867318958634","seed":32575952544210805816121717540196866756760803562104302401499460783867318958634,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"25.adc_ctrl_clock_gating.23932762973362614050869444334667291480525702296219394139451053416295629756529","seed":23932762973362614050869444334667291480525702296219394139451053416295629756529,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"45.adc_ctrl_clock_gating.49917061448511090425965490493769602788031795175288743248972262622042085804121","seed":49917061448511090425965490493769602788031795175288743248972262622042085804121,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"adc_ctrl_clock_gating","qual_name":"1.adc_ctrl_clock_gating.28962709314322086732555850226889067043709568486570841225466203118392047614081","seed":28962709314322086732555850226889067043709568486570841225466203118392047614081,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 1681462346 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 1681462346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"2.adc_ctrl_clock_gating.67518232317425793033424764956362874363160454045287892379463044840769063225092","seed":67518232317425793033424764956362874363160454045287892379463044840769063225092,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 204255554712 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 204255554712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_stress_all_with_rand_reset","qual_name":"2.adc_ctrl_stress_all_with_rand_reset.41355937898791576339303536104881059374287512904656367977242292543271046586620","seed":41355937898791576339303536104881059374287512904656367977242292543271046586620,"line":337,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1672736192 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 1672736192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"9.adc_ctrl_clock_gating.82490988517346629123441018376583846018760078795249995999416850094048164151528","seed":82490988517346629123441018376583846018760078795249995999416850094048164151528,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 1533567043 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 1533567043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_stress_all","qual_name":"11.adc_ctrl_stress_all.6852996096956210789490110438790428386281884323872198036237535744774191499148","seed":6852996096956210789490110438790428386281884323872198036237535744774191499148,"line":336,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 170266087195 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 170266087195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"12.adc_ctrl_clock_gating.55255460403462752400498454927538455194812017460013813527512852055028782729869","seed":55255460403462752400498454927538455194812017460013813527512852055028782729869,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 1980685976 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 1980685976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"13.adc_ctrl_clock_gating.30029395136327729544462281031900142409059197646288303348724086349235159830265","seed":30029395136327729544462281031900142409059197646288303348724086349235159830265,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 395787742130 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 395787742130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"14.adc_ctrl_clock_gating.4965219221292827196064487345421005103288780210651317777881375450958220959932","seed":4965219221292827196064487345421005103288780210651317777881375450958220959932,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 326814795156 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 326814795156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"16.adc_ctrl_clock_gating.84652825777165479200716800902284381995491071633670571261127129381269903592072","seed":84652825777165479200716800902284381995491071633670571261127129381269903592072,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 179569110241 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 179569110241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"18.adc_ctrl_clock_gating.101783217443681340353356389263282768059153846455015242631542539684549132346653","seed":101783217443681340353356389263282768059153846455015242631542539684549132346653,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 2672626105 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 2672626105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"40.adc_ctrl_clock_gating.83832988762994968722188338017991797948129451200563137033009048750894257435537","seed":83832988762994968722188338017991797948129451200563137033009048750894257435537,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 167652858094 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 167652858094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1049,"total":1065,"percent":98.49765258215963}