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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"5.keymgr_stress_all_with_rand_reset.9347857743600183602849842311645915673994927533580807987074573898880680036701","seed":9347857743600183602849842311645915673994927533580807987074573898880680036701,"line":282,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 247471987 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 247471987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"10.keymgr_stress_all_with_rand_reset.30489429405638291791518773126530199542386946838565544717636794139665921835797","seed":30489429405638291791518773126530199542386946838565544717636794139665921835797,"line":251,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 465110656 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 465110656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"12.keymgr_stress_all_with_rand_reset.26161777065651691803564391379924540695407554616962557467030160493096780774953","seed":26161777065651691803564391379924540695407554616962557467030160493096780774953,"line":252,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 267968257 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 267968257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"13.keymgr_stress_all_with_rand_reset.846329129396773658569846784225397833695595717673959328877137487386956506612","seed":846329129396773658569846784225397833695595717673959328877137487386956506612,"line":361,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 431060074 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 431060074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"21.keymgr_stress_all_with_rand_reset.109527120391061349562086489638454696224430055716331489882839881295327020393793","seed":109527120391061349562086489638454696224430055716331489882839881295327020393793,"line":150,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 242557324 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 242557324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"23.keymgr_stress_all_with_rand_reset.106492105456149077072269988376259924862068135475321426394560790350657432425647","seed":106492105456149077072269988376259924862068135475321426394560790350657432425647,"line":173,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 938848239 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 938848239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"25.keymgr_stress_all_with_rand_reset.29299703668857500845186045496298768323277796265128572947409532683945132082747","seed":29299703668857500845186045496298768323277796265128572947409532683945132082747,"line":102,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 511828040 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 511828040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"29.keymgr_stress_all_with_rand_reset.97379852945704047098476689805123983082024619478832998832923944575729817083757","seed":97379852945704047098476689805123983082024619478832998832923944575729817083757,"line":885,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 648484338 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 648484338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.92711885851434745399643523935068786432672716194453231887548931405343501295224","seed":92711885851434745399643523935068786432672716194453231887548931405343501295224,"line":794,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 621219488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 621219488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.103733889665166452228851677466315205239605109534686947104379567909636221421525","seed":103733889665166452228851677466315205239605109534686947104379567909636221421525,"line":197,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 445852847 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 445852847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"37.keymgr_stress_all_with_rand_reset.98858282508426056845087341234918538015080206503136591271512643342182544092133","seed":98858282508426056845087341234918538015080206503136591271512643342182544092133,"line":298,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 493228995 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 493228995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"38.keymgr_stress_all_with_rand_reset.36610238593473911147875066560118661318293547459704724805550076887405897366524","seed":36610238593473911147875066560118661318293547459704724805550076887405897366524,"line":679,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 213137030 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 213137030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"40.keymgr_stress_all_with_rand_reset.26311212931440854657381554684034992024839369826103808579126685094862523928976","seed":26311212931440854657381554684034992024839369826103808579126685094862523928976,"line":191,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 111597509 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 111597509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"41.keymgr_stress_all_with_rand_reset.68420566469213146422084895088128898115444999598460878863220358775705556183944","seed":68420566469213146422084895088128898115444999598460878863220358775705556183944,"line":158,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 997084652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 997084652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.45080781127112453307061382799886684221302824808764916492692612837520324003225","seed":45080781127112453307061382799886684221302824808764916492692612837520324003225,"line":232,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 124982144 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 124982144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"48.keymgr_stress_all_with_rand_reset.113026655030022296229259919214374351775506005235134703125505379800629897492343","seed":113026655030022296229259919214374351775506005235134703125505379800629897492343,"line":455,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2064805737 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2064805737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"49.keymgr_stress_all_with_rand_reset.47229918748145052884897331709142755860032177970828609385812787476408617632819","seed":47229918748145052884897331709142755860032177970828609385812787476408617632819,"line":318,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 663887731 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 663887731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes":[{"name":"keymgr_stress_all","qual_name":"4.keymgr_stress_all.89509725714178672334501768812752505987546650501339974327462640935999064971564","seed":89509725714178672334501768812752505987546650501339974327462640935999064971564,"line":3985,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 823329208 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (711986446759117756801931552182858964782796381723048228553672254915945424806938599085912901254564839009242203214861994742899656410198464036154379860654212 [0xd981e04a621536a20ce47836138322e342e0ffe327b2bd76e55e6e2630dc8ed63c94b9813c6985e056dd15ce5c57d94a5370f8810df5e5756b92cc237ab3884] vs 711986446759117756801931552182858964782796381723048228553672254915945424806938599085912901254564839009242203214861994742899656410198464036154379860654212 [0xd981e04a621536a20ce47836138322e342e0ffe327b2bd76e55e6e2630dc8ed63c94b9813c6985e056dd15ce5c57d94a5370f8810df5e5756b92cc237ab3884]) AES key at state StDisabled for Attestation Aes\n","UVM_INFO @ 823329208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"4.keymgr_stress_all_with_rand_reset.66248113499095597596038601555879083169831623814275255080701059662303072650149","seed":66248113499095597596038601555879083169831623814275255080701059662303072650149,"line":440,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 256199895 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 256199895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"39.keymgr_stress_all.99361129705406457267600298119998277986438086365354261517185231646324118638671","seed":99361129705406457267600298119998277986438086365354261517185231646324118638671,"line":2439,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1387924982 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 1387924982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_sideload","qual_name":"42.keymgr_sideload.50931863785257584068305386481714517998992475602032989565323327016462927221535","seed":50931863785257584068305386481714517998992475602032989565323327016462927221535,"line":124,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_sideload/latest/run.log","log_context":["UVM_ERROR @  18565721 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  18565721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!":[{"name":"keymgr_sync_async_fault_cross","qual_name":"18.keymgr_sync_async_fault_cross.6730407188878785549402547382901955832778638955046510929068380045022298693689","seed":6730407188878785549402547382901955832778638955046510929068380045022298693689,"line":178,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest/run.log","log_context":["UVM_ERROR @ 616165273 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!\n","UVM_INFO @ 616165273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2077,"total":2100,"percent":98.9047619047619}