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":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"kmac_stress_all_with_rand_reset":{"max_time":214.9,"sim_time":0.0,"passed":4,"total":10,"percent":40.0}},"passed":4,"total":10,"percent":40.0}},"passed":4,"total":10,"percent":40.0}},"coverage":{"code":{"block":null,"line_statement":97.7,"branch":96.04,"condition_expression":94.41,"toggle":100.0,"fsm":73.55},"assertion":97.9,"functional":96.54},"cov_report_page":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR 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---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"3.kmac_stress_all_with_rand_reset.31879595300284368973753907273026269640609977553282937262900477130537193861376","seed":31879595300284368973753907273026269640609977553282937262900477130537193861376,"line":266,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9863593674 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0]) \n","UVM_INFO @ 9863593674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"kmac_stress_all_with_rand_reset","qual_name":"1.kmac_stress_all_with_rand_reset.103565501542736280035336657502512762900454356443197196662402930854776763242261","seed":103565501542736280035336657502512762900454356443197196662402930854776763242261,"line":104,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3172112710 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3172112710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"4.kmac_stress_all_with_rand_reset.91780293626671347321969933696931185576685007706941200579832507581682529202698","seed":91780293626671347321969933696931185576685007706941200579832507581682529202698,"line":106,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3230414661 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3230414661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"5.kmac_stress_all_with_rand_reset.83209977267514474369397794840635153132065073798021207738376669607407001113699","seed":83209977267514474369397794840635153132065073798021207738376669607407001113699,"line":126,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 20703800252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 20703800252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_stress_all_with_rand_reset","qual_name":"6.kmac_stress_all_with_rand_reset.73841992393146077550331141760087953966857437245477849323760542247196073869362","seed":73841992393146077550331141760087953966857437245477849323760542247196073869362,"line":96,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1128093436 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1128093436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)":[{"name":"kmac_sideload_invalid","qual_name":"5.kmac_sideload_invalid.80945381262739741241591484343825300627494890165599917943397618115206776232110","seed":80945381262739741241591484343825300627494890165599917943397618115206776232110,"line":80,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10025313968 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb91b7000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)\n","UVM_INFO @ 10025313968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_sideload_invalid","qual_name":"8.kmac_sideload_invalid.11455227739039213271276209862843975212601788562123253508225832596359777299564","seed":11455227739039213271276209862843975212601788562123253508225832596359777299564,"line":80,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10131337146 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc7cbc000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)\n","UVM_INFO @ 10131337146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_sideload_invalid","qual_name":"38.kmac_sideload_invalid.110899232396573554342425840675322335885587818644997138865764812425536410448559","seed":110899232396573554342425840675322335885587818644997138865764812425536410448559,"line":80,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10143183958 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e3d1000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)\n","UVM_INFO @ 10143183958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"kmac_sideload_invalid","qual_name":"11.kmac_sideload_invalid.21009888581961652785641310801862596978259165973460633350744549507439404595471","seed":21009888581961652785641310801862596978259165973460633350744549507439404595471,"line":85,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10152487258 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaaeb2000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)\n","UVM_INFO @ 10152487258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_sideload_invalid","qual_name":"31.kmac_sideload_invalid.6019407250293378010794093149008649827434328811515253018922873410754219781717","seed":6019407250293378010794093149008649827434328811515253018922873410754219781717,"line":85,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10135288571 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf4e3e000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)\n","UVM_INFO @ 10135288571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"kmac_sideload_invalid","qual_name":"18.kmac_sideload_invalid.72128972802711624503147469115224971528118647793156290294343514382392570682228","seed":72128972802711624503147469115224971528118647793156290294343514382392570682228,"line":85,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10090208900 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c005000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)\n","UVM_INFO @ 10090208900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)":[{"name":"kmac_sideload_invalid","qual_name":"23.kmac_sideload_invalid.5790022515479738538574025653095463468104475351455026914606864432357987499867","seed":5790022515479738538574025653095463468104475351455026914606864432357987499867,"line":91,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10137969130 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf9f10000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)\n","UVM_INFO @ 10137969130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"kmac_sideload_invalid","qual_name":"25.kmac_sideload_invalid.109541599814284476786203804517913387828450019640948319643586934601707169252254","seed":109541599814284476786203804517913387828450019640948319643586934601707169252254,"line":79,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10019582423 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x49ec0000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)\n","UVM_INFO @ 10019582423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)":[{"name":"kmac_sideload_invalid","qual_name":"33.kmac_sideload_invalid.34242634853396222093410574810202164750214871333625838633875042297928590291338","seed":34242634853396222093410574810202164750214871333625838633875042297928590291338,"line":78,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10090919593 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd49bb000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)\n","UVM_INFO @ 10090919593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"kmac_sideload_invalid","qual_name":"46.kmac_sideload_invalid.79893277570548109900917409619582020855114567747679908853256690617730201367548","seed":79893277570548109900917409619582020855114567747679908853256690617730201367548,"line":78,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10008667333 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x41348000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)\n","UVM_INFO @ 10008667333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)":[{"name":"kmac_sideload_invalid","qual_name":"43.kmac_sideload_invalid.57654773695693069359847530930772071955043675014605050042288640797244244401029","seed":57654773695693069359847530930772071955043675014605050042288640797244244401029,"line":94,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log","log_context":["UVM_FATAL @ 10443943082 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6ff1a000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)\n","UVM_INFO @ 10443943082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *":[{"name":"kmac_shadow_reg_errors_with_csr_rw","qual_name":"11.kmac_shadow_reg_errors_with_csr_rw.438280977110900780844860290098962149123446200283075129883095371898825155179","seed":438280977110900780844860290098962149123446200283075129883095371898825155179,"line":259,"log_path":"/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 113245850 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2555393414 [0x98503586] vs 3610711141 [0xd7371465]) Regname: kmac_reg_block.prefix_6.prefix_0 reset value: 0x0 \n","UVM_INFO @ 113245850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1467,"total":1485,"percent":98.78787878787878}