{"block":{"name":"lc_ctrl","variant":"volatile_unlock_disabled","commit":"2a8108389bd1d8900602f168b9f28b658865e3c6","commit_short":"2a81083","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/2a8108389bd1d8900602f168b9f28b658865e3c6","revision_info":"GitHub Revision: [`2a81083`](https://github.com/lowrisc/opentitan/tree/2a8108389bd1d8900602f168b9f28b658865e3c6)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-22T00:11:46Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/lc_ctrl_volatile_unlock_disabled/data/lc_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"lc_ctrl_smoke":{"max_time":13.28,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.27,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.22,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"lc_ctrl_csr_bit_bash":{"max_time":1.62,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"lc_ctrl_csr_aliasing":{"max_time":1.7,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"lc_ctrl_csr_mem_rw_with_rand_reset":{"max_time":1.61,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.22,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.7,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":130,"total":130,"percent":100.0},"V2":{"testpoints":{"state_post_trans":{"tests":{"lc_ctrl_state_post_trans":{"max_time":11.35,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"regwen_during_op":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":22.22,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rand_wr_claim_transition_if":{"tests":{"lc_ctrl_claim_transition_if":{"max_time":1.32,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_prog_failure":{"tests":{"lc_ctrl_prog_failure":{"max_time":3.81,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_state_failure":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_errors":{"tests":{"lc_ctrl_errors":{"max_time":14.52,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"security_escalation":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_prog_failure":{"max_time":3.81,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_errors":{"max_time":14.52,"sim_time":0.0,"passed":49,"total":50,"percent":98.0},"lc_ctrl_security_escalation":{"max_time":14.41,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_failure":{"max_time":99.3,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":20.32,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":112.82,"sim_time":0.0,"passed":17,"total":20,"percent":85.0}},"passed":256,"total":260,"percent":98.46153846153847},"jtag_access":{"tests":{"lc_ctrl_jtag_csr_hw_reset":{"max_time":2.76,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_rw":{"max_time":4.18,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_bit_bash":{"max_time":34.93,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_aliasing":{"max_time":11.42,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_same_csr_outstanding":{"max_time":2.2,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_mem_rw_with_rand_reset":{"max_time":3.89,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_alert_test":{"max_time":2.21,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_smoke":{"max_time":13.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":19.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":20.32,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":112.82,"sim_time":0.0,"passed":17,"total":20,"percent":85.0},"lc_ctrl_jtag_access":{"max_time":23.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_regwen_during_op":{"max_time":25.67,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":207,"total":210,"percent":98.57142857142857},"jtag_priority":{"tests":{"lc_ctrl_jtag_priority":{"max_time":20.57,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_ctrl_volatile_unlock":{"tests":{"lc_ctrl_volatile_unlock_smoke":{"max_time":1.68,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"lc_ctrl_stress_all":{"max_time":381.62,"sim_time":0.0,"passed":46,"total":50,"percent":92.0}},"passed":46,"total":50,"percent":92.0},"alert_test":{"tests":{"lc_ctrl_alert_test":{"max_time":1.81,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":3.32,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":3.32,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.27,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.22,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.7,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":1.67,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.27,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.22,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.7,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":1.67,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":978,"total":990,"percent":98.78787878787878},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":3.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":3.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_transition_config_regwen":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":22.22,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_manuf_state_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_manuf_state_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_state_config_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_kmac_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_local_esc":{"tests":{"lc_ctrl_state_failure":{"max_time":14.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":10.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_global_esc":{"tests":{"lc_ctrl_security_escalation":{"max_time":14.41,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_main_ctrl_flow_consistency":{"tests":{"lc_ctrl_state_post_trans":{"max_time":11.35,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":19.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":70,"total":70,"percent":100.0},"sec_cm_intersig_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":17.66,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_ctrl_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":17.66,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_digest":{"tests":{"lc_ctrl_sec_token_digest":{"max_time":16.44,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_mux_ctrl_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":14.66,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_mux_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":14.66,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":865,"total":865,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"lc_ctrl_stress_all_with_rand_reset":{"max_time":144.14,"sim_time":0.0,"passed":25,"total":50,"percent":50.0}},"passed":25,"total":50,"percent":50.0}},"passed":25,"total":50,"percent":50.0}},"coverage":{"code":{"block":null,"line_statement":97.26,"branch":94.27,"condition_expression":81.92,"toggle":89.54,"fsm":68.22},"assertion":94.13,"functional":96.26},"cov_report_page":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"0.lc_ctrl_stress_all_with_rand_reset.105406533713699107250828915707927947930993861796989077282253634944976773257435","seed":105406533713699107250828915707927947930993861796989077282253634944976773257435,"line":1260,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3195364269 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3195364269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"1.lc_ctrl_stress_all_with_rand_reset.60712798075477661671981884980406438933032546336799597991377258546374869277949","seed":60712798075477661671981884980406438933032546336799597991377258546374869277949,"line":7659,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7004049002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7004049002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.25881006449731994115173939853748857731968731358129912523504824909066208889764","seed":25881006449731994115173939853748857731968731358129912523504824909066208889764,"line":158,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4389949599 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4389949599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"5.lc_ctrl_stress_all_with_rand_reset.94060104522983025404298049453452239086915759062487169865475965777558459017207","seed":94060104522983025404298049453452239086915759062487169865475965777558459017207,"line":2777,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16135427419 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16135427419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.93303375268362791472455488945481564303472734486151803962891841250889614060119","seed":93303375268362791472455488945481564303472734486151803962891841250889614060119,"line":225,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 527118728 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 527118728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"10.lc_ctrl_stress_all_with_rand_reset.97673163016107781182540921848417338463581252545085305564312508219592451867584","seed":97673163016107781182540921848417338463581252545085305564312508219592451867584,"line":3870,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2054612861 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2054612861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.21890526891279377706965812568033681601832236819030882069931792031994988103011","seed":21890526891279377706965812568033681601832236819030882069931792031994988103011,"line":6279,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1453210842 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1453210842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"15.lc_ctrl_stress_all_with_rand_reset.111529334366136704774725276070146389662222877647841070691929780391808057619573","seed":111529334366136704774725276070146389662222877647841070691929780391808057619573,"line":3387,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4082532535 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4082532535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.59984721751839732311259553673319744053626271673823744252416635368257842881968","seed":59984721751839732311259553673319744053626271673823744252416635368257842881968,"line":1548,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 508894698 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 508894698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.79897765157169558790757167006108264150822291633194223451567888213392633191421","seed":79897765157169558790757167006108264150822291633194223451567888213392633191421,"line":195,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 424763452 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 424763452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.93158794631239536650439972684580639903077614702198161750628214661086386095509","seed":93158794631239536650439972684580639903077614702198161750628214661086386095509,"line":155,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2724820652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2724820652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"22.lc_ctrl_stress_all_with_rand_reset.61130509527090334329405305675549352359148332039177841229608755916218772144778","seed":61130509527090334329405305675549352359148332039177841229608755916218772144778,"line":6022,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 28809812681 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 28809812681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.69831712453819548067054139988349486412149367279956683251640536908971937672961","seed":69831712453819548067054139988349486412149367279956683251640536908971937672961,"line":1804,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1602280237 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1602280237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.37338706816075463574858624493671582255382514389002445619869475554553713016416","seed":37338706816075463574858624493671582255382514389002445619869475554553713016416,"line":1126,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1955854245 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1955854245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"32.lc_ctrl_stress_all_with_rand_reset.22980245611048238046022801761291761363536216766470469531228212454907626541194","seed":22980245611048238046022801761291761363536216766470469531228212454907626541194,"line":2163,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1997342766 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1997342766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.85761908067448083472226029982965188972455676093414443762350145292498791169650","seed":85761908067448083472226029982965188972455676093414443762350145292498791169650,"line":944,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2400254545 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2400254545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"38.lc_ctrl_stress_all_with_rand_reset.43711683042876567056375947430206808962223505648187807739258891976318104072623","seed":43711683042876567056375947430206808962223505648187807739258891976318104072623,"line":4308,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1813240959 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1813240959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.28813726160564461478545292550434556545674052466273551617696460344733225437466","seed":28813726160564461478545292550434556545674052466273551617696460344733225437466,"line":1383,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13630116342 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 13630116342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.3428585973035125045002660951557601667826729294674519525646624295014279519976","seed":3428585973035125045002660951557601667826729294674519525646624295014279519976,"line":542,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5000724443 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5000724443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.18458687993427206248018060387809141621804919910995941617564916159171818413740","seed":18458687993427206248018060387809141621804919910995941617564916159171818413740,"line":2476,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1164176962 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1164176962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.27725094215578130581363521191135304798116076446068936760212721345694625355386","seed":27725094215578130581363521191135304798116076446068936760212721345694625355386,"line":2792,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17206068352 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17206068352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_jtag_errors","qual_name":"3.lc_ctrl_jtag_errors.69255469760833686096524232700379205731093871122404414230242151045207621920842","seed":69255469760833686096524232700379205731093871122404414230242151045207621920842,"line":510,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 1863315494 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1863315494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"10.lc_ctrl_jtag_errors.39074770573943161142705219707180077085807830068544692133633456749498984855094","seed":39074770573943161142705219707180077085807830068544692133633456749498984855094,"line":2508,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 9576754046 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 9576754046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.28844432952388804411329791834193900701248088832090986460625341391248281232689","seed":28844432952388804411329791834193900701248088832090986460625341391248281232689,"line":8781,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8773566252 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 8773566252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"19.lc_ctrl_jtag_errors.93589266953580167890866915362877670236383817651142728902380542092522793200910","seed":93589266953580167890866915362877670236383817651142728902380542092522793200910,"line":383,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 298298385 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 298298385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"26.lc_ctrl_errors.49140926525233188033430592840574499418751799690243878403030347095471692088672","seed":49140926525233188033430592840574499418751799690243878403030347095471692088672,"line":818,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 652439939 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 652439939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"27.lc_ctrl_stress_all.72179146381413957473266044357237910203993053784948701388924932486397965842471","seed":72179146381413957473266044357237910203993053784948701388924932486397965842471,"line":17596,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6459421550 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 6459421550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"29.lc_ctrl_stress_all.10022267454492857724694983811434261219805338760213138499420961553303029368936","seed":10022267454492857724694983811434261219805338760213138499420961553303029368936,"line":6355,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 14588173072 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 14588173072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"35.lc_ctrl_stress_all.34006085435031588881389424481125457836475729063218215526338395188684596012502","seed":34006085435031588881389424481125457836475729063218215526338395188684596012502,"line":512,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1267200911 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1267200911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"38.lc_ctrl_stress_all.67114493096176560591225140370023701073802397820221528190674287462864733912072","seed":67114493096176560591225140370023701073802397820221528190674287462864733912072,"line":7019,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 8103087357 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 8103087357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.53874771054649559211865533291271361551821956851393014555665745006105461598200","seed":53874771054649559211865533291271361551821956851393014555665745006105461598200,"line":2580,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1166403758 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 1166403758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.5232561720047912503082704640668276548761219776024527306929063511066137271498","seed":5232561720047912503082704640668276548761219776024527306929063511066137271498,"line":18084,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10071458638 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 10071458638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.12159769801289504312282777528357715146675819842027966284601632702705718024268","seed":12159769801289504312282777528357715146675819842027966284601632702705718024268,"line":211,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3837806258 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked3\n","UVM_INFO @ 3837806258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1998,"total":2035,"percent":98.18181818181819}