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---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"47.sram_ctrl_readback_err.103019438271826407923122157806695987882710359187520208893492750744445688485004","seed":103019438271826407923122157806695987882710359187520208893492750744445688485004,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/47.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 5053161072 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x2e)\n","UVM_INFO @ 5053161072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"49.sram_ctrl_readback_err.113935572532870149381849640116952040993310899570345709221426008822615360297987","seed":113935572532870149381849640116952040993310899570345709221426008822615360297987,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/49.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 2984741854 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x13)\n","UVM_INFO @ 2984741854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.88071218548231124371763751608265389365396949059568790028404672780570542053265","seed":88071218548231124371763751608265389365396949059568790028404672780570542053265,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6518169 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   6518169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.22803899868781688785368267878841318669918363686831355752735900536866336896342","seed":22803899868781688785368267878841318669918363686831355752735900536866336896342,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6616136 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   6616136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.32086438446027174143869025076170682845287308510192373754157111887518907691811","seed":32086438446027174143869025076170682845287308510192373754157111887518907691811,"line":103,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   8479190 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   8479190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.23925980354899334238992586538930624912457780628161721860040700941585290076416","seed":23925980354899334238992586538930624912457780628161721860040700941585290076416,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @  21559483 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @  21559483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$isunknown(rdata_o))'":[{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.52195369912248455162090200945301524517972281949726393445030128839043559314829","seed":52195369912248455162090200945301524517972281949726393445030128839043559314829,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @  14869615 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @  14869615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"11.sram_ctrl_mubi_enc_err.31554994595427161180913893715544804332635001058235630445964234030627578891182","seed":31554994595427161180913893715544804332635001058235630445964234030627578891182,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 666325242 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 666325242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"19.sram_ctrl_mubi_enc_err.56562520202558236666852964176369183489334992844393615147054769439923794566611","seed":56562520202558236666852964176369183489334992844393615147054769439923794566611,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/19.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 663630712 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 663630712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"20.sram_ctrl_mubi_enc_err.88308770763810427961092026666885060351646227903578174772263676811939756494840","seed":88308770763810427961092026666885060351646227903578174772263676811939756494840,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/20.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 686858267 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 686858267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"25.sram_ctrl_mubi_enc_err.55690264826279505761955908755920436856549317049227031095673410242135483936611","seed":55690264826279505761955908755920436856549317049227031095673410242135483936611,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/25.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 2739028319 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 2739028319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"40.sram_ctrl_mubi_enc_err.112036170448490763099610079969462613258722738400428065128480195510167709531803","seed":112036170448490763099610079969462613258722738400428065128480195510167709531803,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/40.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 2737203090 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 2737203090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"43.sram_ctrl_mubi_enc_err.89822436853024139704282191077859509692854075847846466726176614152477336569158","seed":89822436853024139704282191077859509692854075847846466726176614152477336569158,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/43.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 3298428318 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 3298428318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"44.sram_ctrl_mubi_enc_err.98662013605858000025007366910643754998341707447667087677132965483754937838998","seed":98662013605858000025007366910643754998341707447667087677132965483754937838998,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/44.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 690651698 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 690651698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"46.sram_ctrl_mubi_enc_err.38904419376307676130347299429694805354017976077815882649729794135399900421315","seed":38904419376307676130347299429694805354017976077815882649729794135399900421315,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/46.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 672525760 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 672525760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":1898,"total":1950,"percent":97.33333333333333}