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[csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"10.sram_ctrl_csr_mem_rw_with_rand_reset.100272840698993129834266789964240393012648873564372554278547694672569345682115","seed":100272840698993129834266789964240393012648873564372554278547694672569345682115,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  97394306 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 \n","UVM_INFO @  97394306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending 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---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"25.sram_ctrl_mubi_enc_err.55321401379797238221911409375737718340846863088887864257129652577138527408445","seed":55321401379797238221911409375737718340846863088887864257129652577138527408445,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  27697823 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  27697823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"27.sram_ctrl_mubi_enc_err.91829964813794995445432418256114521533838056461288531784052531860226376557162","seed":91829964813794995445432418256114521533838056461288531784052531860226376557162,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  45940635 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  45940635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"28.sram_ctrl_mubi_enc_err.60292902555569766392972649604260403020267862325440262626584059824867572895885","seed":60292902555569766392972649604260403020267862325440262626584059824867572895885,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  54128214 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  54128214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"33.sram_ctrl_mubi_enc_err.69585015563851657548487231925177643702050813928473979143440128648491469531746","seed":69585015563851657548487231925177643702050813928473979143440128648491469531746,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  25817861 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  25817861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"34.sram_ctrl_mubi_enc_err.13930933241509528510523632619402216650493383300533408520951018734561355918878","seed":13930933241509528510523632619402216650493383300533408520951018734561355918878,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 110547363 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 110547363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"37.sram_ctrl_mubi_enc_err.57147091825591356734941254291425456158327255257311360608710500697236711239249","seed":57147091825591356734941254291425456158327255257311360608710500697236711239249,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  33104292 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  33104292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"38.sram_ctrl_mubi_enc_err.33305628271992450261471093063017413956360167061331095521523093622706471620251","seed":33305628271992450261471093063017413956360167061331095521523093622706471620251,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  30914237 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  30914237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"47.sram_ctrl_mubi_enc_err.16667493035970472026827379574175045824411693242126618256371285172996155049868","seed":16667493035970472026827379574175045824411693242126618256371285172996155049868,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  30449701 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  30449701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.43189735976129872281520705707583577312127361710204026799935314804228535069414","seed":43189735976129872281520705707583577312127361710204026799935314804228535069414,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6353582 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   6353582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.86500642893050238013100590096465118393083421449799653527319107998737072850830","seed":86500642893050238013100590096465118393083421449799653527319107998737072850830,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6429995 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   6429995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.84132652994227545592926519425511091407770369733676132759122991462928957926701","seed":84132652994227545592926519425511091407770369733676132759122991462928957926701,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   1930087 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   1930087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"1.sram_ctrl_readback_err.31802671693235367741334154825236367001741827445499644270943813336824470483778","seed":31802671693235367741334154825236367001741827445499644270943813336824470483778,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  90810687 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x72)\n","UVM_INFO @  90810687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"13.sram_ctrl_readback_err.8222622998165749419421404975471546663524066004043337396506739107047259802509","seed":8222622998165749419421404975471546663524066004043337396506739107047259802509,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  23339059 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x6c)\n","UVM_INFO @  23339059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"15.sram_ctrl_readback_err.36626495992814916421797425010750250781638174902163318812018128690680730990463","seed":36626495992814916421797425010750250781638174902163318812018128690680730990463,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  87717856 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x32) != exp (0x28)\n","UVM_INFO @  87717856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"19.sram_ctrl_readback_err.72203035502371235145318861909820067933794008692456191323862728567873669489450","seed":72203035502371235145318861909820067933794008692456191323862728567873669489450,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  45812099 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x11)\n","UVM_INFO @  45812099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"23.sram_ctrl_readback_err.100236543822270653179899511953483157973311135622938620473810779039989067563844","seed":100236543822270653179899511953483157973311135622938620473810779039989067563844,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/23.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  46217750 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x79)\n","UVM_INFO @  46217750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"25.sram_ctrl_readback_err.110770636629829299873138741056155346573193201792627304559600915097351322576297","seed":110770636629829299873138741056155346573193201792627304559600915097351322576297,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/25.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 106976575 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x41)\n","UVM_INFO @ 106976575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"26.sram_ctrl_readback_err.35328217609336680027111961418719354395450849132747317670532844998422074309239","seed":35328217609336680027111961418719354395450849132747317670532844998422074309239,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/26.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  31711256 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x8)\n","UVM_INFO @  31711256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"39.sram_ctrl_readback_err.89914707877401449736147662327791169259933883326015824533300150684543642882824","seed":89914707877401449736147662327791169259933883326015824533300150684543642882824,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/39.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  24139192 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5f) != exp (0x55)\n","UVM_INFO @  24139192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(depth_o <= *'(Depth))'":[{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.40720085178367727567446173267803174115927300564259280017800333648807417971940","seed":40720085178367727567446173267803174115927300564259280017800333648807417971940,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(depth_o <= 2'(Depth))'\n","UVM_ERROR @   1843276 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth\n","UVM_INFO @   1843276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.108141320097822087456748753863130965860869736975180674992708049322060287749702","seed":108141320097822087456748753863130965860869736975180674992708049322060287749702,"line":101,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(depth_o <= 2'(Depth))'\n","UVM_ERROR @   4723876 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth\n","UVM_INFO @   4723876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"3.sram_ctrl_stress_all_with_rand_reset.13103210087767966416050926487435736678198948017183779730354962046601005063177","seed":13103210087767966416050926487435736678198948017183779730354962046601005063177,"line":110,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 850704322 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 850704322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"41.sram_ctrl_mubi_enc_err.37082272826300127273820473261288685131493239418079025081427360631302620769451","seed":37082272826300127273820473261288685131493239418079025081427360631302620769451,"line":103,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["UVM_ERROR @  29416720 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).\n"," TL item was: req: (cip_tl_seq_item@4497) { a_addr: 'hb91fd68  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5c  a_opcode: 'h4  a_user: 'h2452a  d_param: 'h0  d_source: 'h5c  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @  29416720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}]}},"passed":1899,"total":1950,"percent":97.38461538461539}