{"block":{"name":"sysrst_ctrl","variant":null,"commit":"2a8108389bd1d8900602f168b9f28b658865e3c6","commit_short":"2a81083","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/2a8108389bd1d8900602f168b9f28b658865e3c6","revision_info":"GitHub Revision: [`2a81083`](https://github.com/lowrisc/opentitan/tree/2a8108389bd1d8900602f168b9f28b658865e3c6)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-22T00:11:46Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":8.94,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":10.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":4.53,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":4.82,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":21.91,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":141.96,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":15.72,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":8.54,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":15.72,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":190,"total":190,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":530.94,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":483.06,"sim_time":0.0,"passed":93,"total":100,"percent":93.0}},"passed":93,"total":100,"percent":93.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":657.39,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":253.80999999999997,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":10.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":9.46,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":2024.4900000000002,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":10.4,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":888.15,"sim_time":0.0,"passed":36,"total":50,"percent":72.0}},"passed":36,"total":50,"percent":72.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":76.82,"sim_time":0.0,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":496.43999999999994,"sim_time":0.0,"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":8.12,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":8.59,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.53,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.53,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":21.91,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":15.72,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":36.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":21.91,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":15.72,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":36.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":766,"total":792,"percent":96.71717171717172},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":68.63,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":122.93,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":122.93,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":45,"total":45,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":26.63,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0}},"coverage":{"code":{"block":null,"line_statement":99.4,"branch":99.52,"condition_expression":98.06,"toggle":100.0,"fsm":96.15},"assertion":98.18,"functional":92.13},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"0.sysrst_ctrl_combo_detect_with_pre_cond.17897594844081104396140136854483623488162740102781410887183124691842920834639","seed":17897594844081104396140136854483623488162740102781410887183124691842920834639,"line":672,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 24431041014 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4 \n","UVM_ERROR @ 24431041014 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4 \n","UVM_INFO @ 24431041014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"49.sysrst_ctrl_combo_detect_with_pre_cond.114233619045391368800812024830882274767057651937835058650780899135694135518253","seed":114233619045391368800812024830882274767057651937835058650780899135694135518253,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13078907761 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4 \n","UVM_ERROR @ 13078907761 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4 \n","UVM_INFO @ 13078907761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_stress_all","qual_name":"0.sysrst_ctrl_stress_all.104142978977019907179616930364252141759772690948712740587654516279581665955588","seed":104142978977019907179616930364252141759772690948712740587654516279581665955588,"line":678,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 38738836107 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 38738856107 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 38738856107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"3.sysrst_ctrl_stress_all.13660079820471244891503607029018628784062822684802580741504819171168946888047","seed":13660079820471244891503607029018628784062822684802580741504819171168946888047,"line":685,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 54145390274 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 54145410274 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 54145410274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"11.sysrst_ctrl_ultra_low_pwr.8504515643884367052516954947771409976975556475172333506708599218042547721711","seed":8504515643884367052516954947771409976975556475172333506708599218042547721711,"line":651,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5369331003 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 5369414337 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5369414337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"24.sysrst_ctrl_ultra_low_pwr.26803761081888281379029673402828700556660752821980585198991263787136860642204","seed":26803761081888281379029673402828700556660752821980585198991263787136860642204,"line":651,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4752977719 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4753077719 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4753077719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"26.sysrst_ctrl_ultra_low_pwr.24733338984567319993858116720869592996870065053996460449392041627565961448762","seed":24733338984567319993858116720869592996870065053996460449392041627565961448762,"line":651,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2859007680 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 2859087680 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2859087680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"27.sysrst_ctrl_edge_detect.59325357590121139405798449347465755203755343521619804154587544345361004404843","seed":59325357590121139405798449347465755203755343521619804154587544345361004404843,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2281260510 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 2281301326 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2281301326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"28.sysrst_ctrl_ultra_low_pwr.11845595527340415063754881081890912782575675162806229113086859628197815408395","seed":11845595527340415063754881081890912782575675162806229113086859628197815408395,"line":652,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3737066636 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 3737191636 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3737191636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"36.sysrst_ctrl_ultra_low_pwr.42046287862546514544983783272618607049636442300471042985900381130782176953567","seed":42046287862546514544983783272618607049636442300471042985900381130782176953567,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3729894869 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 3730048715 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3730048715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"38.sysrst_ctrl_ultra_low_pwr.72868012267976106048174375609355352196997871634180048945348361412074533361318","seed":72868012267976106048174375609355352196997871634180048945348361412074533361318,"line":651,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 255456172447 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 255456236963 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 255456236963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"42.sysrst_ctrl_edge_detect.40790852044885891285647052474967686754250075518591372147217377131331823682544","seed":40790852044885891285647052474967686754250075518591372147217377131331823682544,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3229858374 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 3229878576 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3229878576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"44.sysrst_ctrl_ultra_low_pwr.42585825831989115609495370015786501645800420750134138922716407949763752762557","seed":42585825831989115609495370015786501645800420750134138922716407949763752762557,"line":652,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4830404279 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4830445095 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4830445095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"44.sysrst_ctrl_stress_all_with_rand_reset.80208954602288369843023509972959715166345497405354854319276312852666149191200","seed":80208954602288369843023509972959715166345497405354854319276312852666149191200,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7628496174 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 7628576174 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 7628576174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.82092663070951618741133619962716731208882191398124655772969166830904574684101","seed":82092663070951618741133619962716731208882191398124655772969166830904574684101,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2304782347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_ERROR @ 2662282347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 2662282347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"16.sysrst_ctrl_ultra_low_pwr.113247728762891940339272205211507362319357559704393839175407037146816470892555","seed":113247728762891940339272205211507362319357559704393839175407037146816470892555,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2929531989 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_ERROR @ 4777031989 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 4777031989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"18.sysrst_ctrl_stress_all.93328498659274994119978522773954076117048658283850439797796669964313672670289","seed":93328498659274994119978522773954076117048658283850439797796669964313672670289,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 10193528213 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 10501028213 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 12621028213 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 12651308203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"19.sysrst_ctrl_ultra_low_pwr.85801108299886340383614734267813895439538281806970548262533940326286958034871","seed":85801108299886340383614734267813895439538281806970548262533940326286958034871,"line":652,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 6414719519 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 6592219519 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 7997219519 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 8009582842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"31.sysrst_ctrl_ultra_low_pwr.97731029035702910381214728760808508267718325721288768380202306683028518684919","seed":97731029035702910381214728760808508267718325721288768380202306683028518684919,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2284820151 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 2417320151 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 7687320151 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7697256143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"42.sysrst_ctrl_ultra_low_pwr.17237542364943753489071746549850986959371656188434642947840678459010103191187","seed":17237542364943753489071746549850986959371656188434642947840678459010103191187,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2227921750 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 2300421750 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 3710421750 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 7100421750 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7116337596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"43.sysrst_ctrl_ultra_low_pwr.14454814616153104440839308022179307088661087151650251867308101959241842031319","seed":14454814616153104440839308022179307088661087151650251867308101959241842031319,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 6034615476 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 6357115476 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 6937115476 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 6950331826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL (cip_base_vseq.sv:892) [sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"9.sysrst_ctrl_ultra_low_pwr.65095832278263354262070496532566778983807294547199473842285854643168827258862","seed":65095832278263354262070496532566778983807294547199473842285854643168827258862,"line":651,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_FATAL @ 15674517294 ps: (cip_base_vseq.sv:892) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!\n","UVM_INFO @ 15674517294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"21.sysrst_ctrl_combo_detect_with_pre_cond.94772446614674641326004853561958063604060125058249253220237200076173020470309","seed":94772446614674641326004853561958063604060125058249253220237200076173020470309,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 26758661861 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_ERROR @ 26758661861 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 26758661861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"93.sysrst_ctrl_combo_detect_with_pre_cond.71857867808443637144360408308372584411993541421865335635983519939384737927153","seed":71857867808443637144360408308372584411993541421865335635983519939384737927153,"line":687,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 55468698543 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 55483698543 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 55503698543 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 65764137140 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e\n","UVM_INFO @ 65764157548 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2d\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"47.sysrst_ctrl_combo_detect_with_pre_cond.86499771478397652831236760816317578489492580590339662039972523006044122670858","seed":86499771478397652831236760816317578489492580590339662039972523006044122670858,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 24492326254 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-4 \n","UVM_INFO @ 34754380830 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f\n","UVM_INFO @ 34754526668 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x21\n","UVM_INFO @ 35097995992 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3\n","UVM_INFO @ 35112326254 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1b\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"53.sysrst_ctrl_combo_detect_with_pre_cond.43728530664026331725685689073343990336137650606977091091566059199598564696158","seed":43728530664026331725685689073343990336137650606977091091566059199598564696158,"line":713,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 104825023910 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-4 \n","UVM_ERROR @ 104825023910 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-4 \n","UVM_INFO @ 104825023910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"56.sysrst_ctrl_combo_detect_with_pre_cond.49439732885397284910036285978995059270627672983176429589283980931247843652581","seed":49439732885397284910036285978995059270627672983176429589283980931247843652581,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 18529383962 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_ERROR @ 18719516750 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2]) \n","UVM_INFO @ 18719516750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":1050,"total":1077,"percent":97.49303621169916}