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---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"14.adc_ctrl_clock_gating.58670149076492842182358669831573825160621049867020171662450728195949921218387","seed":58670149076492842182358669831573825160621049867020171662450728195949921218387,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 217803677715 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 217803677715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_stress_all_with_rand_reset","qual_name":"19.adc_ctrl_stress_all_with_rand_reset.29461176022705925253769704425146874831662578089568566628939842804862703471661","seed":29461176022705925253769704425146874831662578089568566628939842804862703471661,"line":323,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2049020111 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 2049020111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_stress_all_with_rand_reset","qual_name":"21.adc_ctrl_stress_all_with_rand_reset.1109865927285644755750103029865344876955926595331222550820291144135610353708","seed":1109865927285644755750103029865344876955926595331222550820291144135610353708,"line":385,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 19886163908 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 19886163908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"23.adc_ctrl_clock_gating.113030740223710068177257983466752426407895632215660344881694845571109674035856","seed":113030740223710068177257983466752426407895632215660344881694845571109674035856,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 1698106381 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 1698106381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"24.adc_ctrl_clock_gating.61876229571178695301427543768736725751291983497852567611992449058713194195248","seed":61876229571178695301427543768736725751291983497852567611992449058713194195248,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 207132207397 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 207132207397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_stress_all","qual_name":"31.adc_ctrl_stress_all.84975392418466871252322172114380369810764250491519069744202843999910822169176","seed":84975392418466871252322172114380369810764250491519069744202843999910822169176,"line":345,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 113957149695 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 113957149695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"32.adc_ctrl_clock_gating.102537378449507723090955294143017656696826737831350226536494734084423372293356","seed":102537378449507723090955294143017656696826737831350226536494734084423372293356,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 2293399548 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 2293399548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"47.adc_ctrl_clock_gating.91276219347660572484584578784485203356183902340978684694175047193414587773584","seed":91276219347660572484584578784485203356183902340978684694175047193414587773584,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 179156738071 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 179156738071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"49.adc_ctrl_clock_gating.60193069242155544183830735999178744406408408920383693176101261877379954975292","seed":60193069242155544183830735999178744406408408920383693176101261877379954975292,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_ERROR @ 15871289816 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 15871289816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"adc_ctrl_clock_gating","qual_name":"2.adc_ctrl_clock_gating.78032933326113763286318835791633886710274907441076715826797411583445793466600","seed":78032933326113763286318835791633886710274907441076715826797411583445793466600,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_filters_both","qual_name":"5.adc_ctrl_filters_both.14221911034528428524241379276042153584841588403963157116440676212329799889545","seed":14221911034528428524241379276042153584841588403963157116440676212329799889545,"line":349,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"8.adc_ctrl_clock_gating.110219644049010899806942125917553808181387811306190586682171132706687529400970","seed":110219644049010899806942125917553808181387811306190586682171132706687529400970,"line":351,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"15.adc_ctrl_clock_gating.2280032211044005386505439752940049826679739831016942463241687116613784152181","seed":2280032211044005386505439752940049826679739831016942463241687116613784152181,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"19.adc_ctrl_clock_gating.15615682196057255895293031681882428080440215319709598329970275350390236068996","seed":15615682196057255895293031681882428080440215319709598329970275350390236068996,"line":334,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"adc_ctrl_clock_gating","qual_name":"21.adc_ctrl_clock_gating.17352418008743774320737345412649979671804600572889109296822511418072678595200","seed":17352418008743774320737345412649979671804600572889109296822511418072678595200,"line":317,"log_path":"/nightly/current_run/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1049,"total":1065,"percent":98.49765258215963}