{"block":{"name":"clkmgr","variant":null,"commit":"34fa6f9bc35e15dc92c9ad207268e94b88162789","commit_short":"34fa6f9","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789","revision_info":"GitHub Revision: [`34fa6f9`](https://github.com/lowrisc/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-29T00:12:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":1.45,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.89,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":8.39,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.66,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":130,"total":130,"percent":100.0},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.15,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":1.74,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"extclk":{"tests":{"clkmgr_extclk":{"max_time":1.69,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.09,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":1.45,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":13.47,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":11.62,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":13.47,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":52.01,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.38,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.89,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.89,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":640,"total":640,"percent":100.0},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_tl_intg_err":{"max_time":4.21,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_sec_cm":{"max_time":3.46,"sim_time":0.0,"passed":3,"total":5,"percent":60.0}},"passed":23,"total":25,"percent":92.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":3.06,"sim_time":0.0,"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":4.21,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":13.47,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":11.62,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":1.97,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_ctrl_intersig_mubi":{"tests":{"clkmgr_lc_ctrl_intersig_mubi":{"max_time":1.3,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_ctrl_clk_handshake_intersig_mubi":{"tests":{"clkmgr_lc_clk_byp_req_intersig_mubi":{"max_time":1.4,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_clk_handshake_intersig_mubi":{"tests":{"clkmgr_clk_handshake_intersig_mubi":{"max_time":1.38,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sec_cm_div_intersig_mubi":{"tests":{"clkmgr_div_intersig_mubi":{"max_time":1.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":3.46,"sim_time":0.0,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.16,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":3.46,"sim_time":0.0,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0}},"passed":574,"total":585,"percent":98.11965811965813},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":5.59,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":149.72,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.33,"branch":99.15,"condition_expression":96.18,"toggle":100.0,"fsm":100.0},"assertion":96.47,"functional":87.82},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.80404167305214546283793073228230087014523829649151546577981800899512834426986","seed":80404167305214546283793073228230087014523829649151546577981800899512834426986,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10784214 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: 0x0  Write_and_check_update_error task: check storage_err status\n","UVM_INFO @  10784214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.95332638060476628151417976986935266314607655746747445966163531860622188596896","seed":95332638060476628151417976986935266314607655746747445966163531860622188596896,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 128517679 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!\n","UVM_INFO @ 128517679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.46573218313795862594637892693844980112799008138661791576563739755806131974348","seed":46573218313795862594637892693844980112799008138661791576563739755806131974348,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 164699292 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!\n","UVM_INFO @ 164699292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.2152318794359197379683116279392857067335475227043473992954104711312135944480","seed":2152318794359197379683116279392857067335475227043473992954104711312135944480,"line":121,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  62794140 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  62794140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"2.clkmgr_sec_cm.16005392208851034890776809140564555787202957640608927932212947942494223598917","seed":16005392208851034890776809140564555787202957640608927932212947942494223598917,"line":94,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  22990806 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  22990806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch":[{"name":"clkmgr_clk_handshake_intersig_mubi","qual_name":"18.clkmgr_clk_handshake_intersig_mubi.107525696663098885888751955002214029967378785418552437738288528547120089948172","seed":107525696663098885888751955002214029967378785418552437738288528547120089948172,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest/run.log","log_context":["UVM_ERROR @   4103546 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (3 [0x3] vs 9 [0x9]) extclk_status mismatch\n","UVM_INFO @   4103546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_clk_handshake_intersig_mubi","qual_name":"36.clkmgr_clk_handshake_intersig_mubi.20729418112844571004046178496535362027423089649856212952056930135600188610253","seed":20729418112844571004046178496535362027423089649856212952056930135600188610253,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest/run.log","log_context":["UVM_ERROR @  60841102 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch\n","UVM_INFO @  60841102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1444,"total":1455,"percent":99.24398625429554}