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---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"4.keymgr_stress_all.113948687223898942926204339907250227842473449334279765608743268331343477407397","seed":113948687223898942926204339907250227842473449334279765608743268331343477407397,"line":206,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 200943832 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 200943832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_hwsw_invalid_input","qual_name":"17.keymgr_hwsw_invalid_input.86802255761187099892317236746174817408241762465018160250630631601083055593995","seed":86802255761187099892317236746174817408241762465018160250630631601083055593995,"line":96,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest/run.log","log_context":["UVM_ERROR @   6414453 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   6414453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"40.keymgr_stress_all.23807042807827092882352126763635428349407294310372096334134425688995350061233","seed":23807042807827092882352126763635428349407294310372096334134425688995350061233,"line":1505,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 747467725 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 747467725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding 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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"6.keymgr_stress_all_with_rand_reset.59966671731767902073821399615022948576346717512485827945193089788079452072273","seed":59966671731767902073821399615022948576346717512485827945193089788079452072273,"line":436,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 280888491 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 280888491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"8.keymgr_stress_all_with_rand_reset.60616770795332798483174053140292639859124509096615389949696383996382078582425","seed":60616770795332798483174053140292639859124509096615389949696383996382078582425,"line":603,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1381376179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1381376179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.68025988113734451747595325622062890385240094044602611143885488103916710013837","seed":68025988113734451747595325622062890385240094044602611143885488103916710013837,"line":185,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 227185352 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 227185352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"15.keymgr_stress_all_with_rand_reset.48838015214136717651839337465123375181872324362325859415146183064095241802485","seed":48838015214136717651839337465123375181872324362325859415146183064095241802485,"line":142,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 328508636 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 328508636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"18.keymgr_stress_all_with_rand_reset.85958579171532170521298888871633592538405007940381452778042583716212029056430","seed":85958579171532170521298888871633592538405007940381452778042583716212029056430,"line":334,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 118368987 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 118368987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"25.keymgr_stress_all_with_rand_reset.79503026610984931149746997952320085859489609003052497738279738465139529109780","seed":79503026610984931149746997952320085859489609003052497738279738465139529109780,"line":169,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 101842339 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 101842339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"26.keymgr_stress_all_with_rand_reset.85823970401244727112588413690053497176226056881627359339863387595176832831394","seed":85823970401244727112588413690053497176226056881627359339863387595176832831394,"line":242,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 109424983 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 109424983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"29.keymgr_stress_all_with_rand_reset.33938567549546685755601825147396799677043278385310894977448919071935880883730","seed":33938567549546685755601825147396799677043278385310894977448919071935880883730,"line":148,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 597193103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 597193103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"30.keymgr_stress_all_with_rand_reset.18696091245296589344669627045130089594077720747003590536629303279021285757315","seed":18696091245296589344669627045130089594077720747003590536629303279021285757315,"line":602,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1644059040 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1644059040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.26878245846397815624848188531280954496305667773709097353809646334613054112345","seed":26878245846397815624848188531280954496305667773709097353809646334613054112345,"line":396,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 174658552 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 174658552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"39.keymgr_stress_all_with_rand_reset.79881329458732038977754768869677928912461857032385695350105322434087749405932","seed":79881329458732038977754768869677928912461857032385695350105322434087749405932,"line":142,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 111601047 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 111601047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"40.keymgr_stress_all_with_rand_reset.29555829177147575788869724737130396281498230475415637911798238027156488594652","seed":29555829177147575788869724737130396281498230475415637911798238027156488594652,"line":282,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 257266699 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 257266699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"41.keymgr_stress_all_with_rand_reset.35292669509543144651837211561172640822050414045596597974799277820118596757510","seed":35292669509543144651837211561172640822050414045596597974799277820118596757510,"line":182,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 138674220 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 138674220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"43.keymgr_stress_all_with_rand_reset.103688159315048663491665682139984845687758983562879195585451100914866427883920","seed":103688159315048663491665682139984845687758983562879195585451100914866427883920,"line":88,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 119125961 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 119125961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"44.keymgr_stress_all_with_rand_reset.103268429961496889796908525113716097690872125688470996677867506103772369776531","seed":103268429961496889796908525113716097690872125688470996677867506103772369776531,"line":717,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 604567432 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 604567432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"46.keymgr_stress_all_with_rand_reset.22272522409992198068100718166130871596618282572141040934556731814452861181847","seed":22272522409992198068100718166130871596618282572141040934556731814452861181847,"line":128,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 110092116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 110092116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"48.keymgr_stress_all_with_rand_reset.33341508535660278063700243845631710901626302290170502138536867696304314319063","seed":33341508535660278063700243845631710901626302290170502138536867696304314319063,"line":847,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 950377480 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 950377480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly":[{"name":"keymgr_kmac_rsp_err","qual_name":"11.keymgr_kmac_rsp_err.80189145966483107856313018460874119944952467797263859086093870284837595901582","seed":80189145966483107856313018460874119944952467797263859086093870284837595901582,"line":357,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest/run.log","log_context":["UVM_ERROR @  22372996 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly\n","UVM_INFO @  22372996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start":[{"name":"keymgr_cfg_regwen","qual_name":"37.keymgr_cfg_regwen.26888539964990888049451371257491837583012471998438068777740232180468796661332","seed":26888539964990888049451371257491837583012471998438068777740232180468796661332,"line":264,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @  44906867 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start\n","UVM_INFO @  44906867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2068,"total":2100,"percent":98.47619047619048}