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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.37828229169025080648025693938829609394012291781257198886003618461350708890539","seed":37828229169025080648025693938829609394012291781257198886003618461350708890539,"line":430,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1029804259 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1029804259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"4.lc_ctrl_stress_all_with_rand_reset.91905614404140346791090142741511769518606969979646543011839913561248813384361","seed":91905614404140346791090142741511769518606969979646543011839913561248813384361,"line":3508,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 18712523437 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 18712523437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.95665357339663988300119678905720444119552835948573528201121171392354225635697","seed":95665357339663988300119678905720444119552835948573528201121171392354225635697,"line":6197,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8960659463 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8960659463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"7.lc_ctrl_stress_all_with_rand_reset.115211938067492259436133750883982402602374221817317114401850474241857136567255","seed":115211938067492259436133750883982402602374221817317114401850474241857136567255,"line":6549,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8751835039 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8751835039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.41562424942025920123329453049066273452486318869358555840826433792704654648993","seed":41562424942025920123329453049066273452486318869358555840826433792704654648993,"line":863,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4225300767 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4225300767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"10.lc_ctrl_stress_all_with_rand_reset.72950030790696916701725675108634706642270135765042987139283544781251324334570","seed":72950030790696916701725675108634706642270135765042987139283544781251324334570,"line":6218,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2367289948 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2367289948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.21219634933159027922769834147461681790897903540298830389682850122911592554143","seed":21219634933159027922769834147461681790897903540298830389682850122911592554143,"line":1166,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 412491748 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 412491748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.43155583060127740723318005886594635452126443162088828872353942895873000307869","seed":43155583060127740723318005886594635452126443162088828872353942895873000307869,"line":4274,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10639408322 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10639408322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.102720805225733257955976662416166856245959354504332719481280591265352735682302","seed":102720805225733257955976662416166856245959354504332719481280591265352735682302,"line":2574,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3640149638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3640149638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.71203841390508010515112653976688448734518906236293386958509570374816812967939","seed":71203841390508010515112653976688448734518906236293386958509570374816812967939,"line":1969,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1102904033 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1102904033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"23.lc_ctrl_stress_all_with_rand_reset.58798438247226342989246744445256280588169781427933793541553443097422839866121","seed":58798438247226342989246744445256280588169781427933793541553443097422839866121,"line":4502,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3631974183 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3631974183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.19213816170992698203200700481632009680458634445732932533764368383093691542321","seed":19213816170992698203200700481632009680458634445732932533764368383093691542321,"line":152,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 493384626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 493384626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.53050151843722333087151924481094997414781305529697851574304448315755907632629","seed":53050151843722333087151924481094997414781305529697851574304448315755907632629,"line":1890,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17080938992 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17080938992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.52176901769187224538967638087532434950186941860859345105855636915990165796684","seed":52176901769187224538967638087532434950186941860859345105855636915990165796684,"line":736,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3867300112 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3867300112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.110015169209441498246705761593496073456151080090596152078314637163515901193880","seed":110015169209441498246705761593496073456151080090596152078314637163515901193880,"line":3107,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4977672261 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4977672261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.62292799361229068021065019683238608605507174162926948205374856618542353232236","seed":62292799361229068021065019683238608605507174162926948205374856618542353232236,"line":5936,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 12926054207 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 12926054207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.15937965872383384594863903797929719273125469938524349916345461539622255949994","seed":15937965872383384594863903797929719273125469938524349916345461539622255949994,"line":3937,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2670057795 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2670057795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.91557740299612667768284587776307015715391945569226035714261185041660047686050","seed":91557740299612667768284587776307015715391945569226035714261185041660047686050,"line":195,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 206347489 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 206347489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.59788942856570319496925786109395610465435832203168368596104145385370341254399","seed":59788942856570319496925786109395610465435832203168368596104145385370341254399,"line":843,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1157537011 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1157537011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.22729236481729916377392638061734098482011970091527230557969924203431107117639","seed":22729236481729916377392638061734098482011970091527230557969924203431107117639,"line":10380,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4647852019 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4647852019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.88523961170336682997399997800218925328279897643745759455654953620450391733836","seed":88523961170336682997399997800218925328279897643745759455654953620450391733836,"line":8335,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2003445742 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2003445742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.22885782307493178425186779932552608110544361579000323778969340604622715279015","seed":22885782307493178425186779932552608110544361579000323778969340604622715279015,"line":5457,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7125971941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7125971941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.25106655459477080148863058460620673726702204380437442363400357186920090972559","seed":25106655459477080148863058460620673726702204380437442363400357186920090972559,"line":626,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 629283523 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 629283523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"49.lc_ctrl_stress_all_with_rand_reset.102426907781480266031314426723162654570238305299137504646117634091702994925861","seed":102426907781480266031314426723162654570238305299137504646117634091702994925861,"line":11625,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 12127959166 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 12127959166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"1.lc_ctrl_stress_all_with_rand_reset.113522482838339978597489627400933211613329834206535869161055378582993456427707","seed":113522482838339978597489627400933211613329834206535869161055378582993456427707,"line":1285,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1895623017 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 1895623017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_errors","qual_name":"4.lc_ctrl_errors.103537572851157324679932558959436849498289666491329357117024736967886408440030","seed":103537572851157324679932558959436849498289666491329357117024736967886408440030,"line":1342,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @  98047533 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  98047533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"12.lc_ctrl_errors.16431431579075463725689146038863973809732551434562152286034444002193913084728","seed":16431431579075463725689146038863973809732551434562152286034444002193913084728,"line":2438,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 274737931 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 274737931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"12.lc_ctrl_stress_all.4619800877407313236016301477217117954442186348254690145690118206537755588985","seed":4619800877407313236016301477217117954442186348254690145690118206537755588985,"line":3907,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1097439861 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1097439861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"14.lc_ctrl_jtag_errors.15084096308767154876577902201533229129457267573802365475381972920376307804214","seed":15084096308767154876577902201533229129457267573802365475381972920376307804214,"line":3500,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 7299662013 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 7299662013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"14.lc_ctrl_stress_all.26428142046324701098191234070307127921466918925470060210937785627387062688952","seed":26428142046324701098191234070307127921466918925470060210937785627387062688952,"line":6494,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 18091673764 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 18091673764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"28.lc_ctrl_errors.92899317943559852506467302275522696109694491849397425550596878649886396351229","seed":92899317943559852506467302275522696109694491849397425550596878649886396351229,"line":4029,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 247700731 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 247700731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.28885348553211235479241717250092710221374187964777541620612409159551823189314","seed":28885348553211235479241717250092710221374187964777541620612409159551823189314,"line":246,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13686907 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked0\n","UVM_INFO @  13686907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1998,"total":2035,"percent":98.18181818181819}