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---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"5.lc_ctrl_errors.15101460693318000742558404483247594524310670239430451152367430088748493630525","seed":15101460693318000742558404483247594524310670239430451152367430088748493630525,"line":4033,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 269087396 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 269087396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.101558327319415869708155932952823971533600781775293140227045631514897607006291","seed":101558327319415869708155932952823971533600781775293140227045631514897607006291,"line":12539,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17037546705 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 17037546705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"17.lc_ctrl_jtag_errors.104997317373878357814552030600444875119012190594549866245634098084205873861107","seed":104997317373878357814552030600444875119012190594549866245634098084205873861107,"line":2407,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 1730756806 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1730756806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.85659205588976588282949051359644932128498755631872316737690001091898938155863","seed":85659205588976588282949051359644932128498755631872316737690001091898938155863,"line":3196,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 763994659 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 763994659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] 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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"32.lc_ctrl_stress_all_with_rand_reset.12137827263092138102809798082263015625680104805221008162503870466507021936524","seed":12137827263092138102809798082263015625680104805221008162503870466507021936524,"line":7281,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5366635100 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 5366635100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.8069984276010300658439405918957133782465244023394782841777117799546134987063","seed":8069984276010300658439405918957133782465244023394782841777117799546134987063,"line":6634,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4129516722 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 4129516722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.41332225963348028477327584702340080389665505965289965755676813262223532809788","seed":41332225963348028477327584702340080389665505965289965755676813262223532809788,"line":6374,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 27528204776 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 27528204776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"5.lc_ctrl_stress_all_with_rand_reset.18020396298825025753776202601584366090889453390490602430875438395720662355023","seed":18020396298825025753776202601584366090889453390490602430875438395720662355023,"line":10904,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4391117305 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4391117305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.86685541143621300176222629514382995297528034067254551255797698665843737259614","seed":86685541143621300176222629514382995297528034067254551255797698665843737259614,"line":7173,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10897435033 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10897435033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.46301321926631277822099233022523402240081147729990792685733996628446557467689","seed":46301321926631277822099233022523402240081147729990792685733996628446557467689,"line":14439,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1702661361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1702661361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.97486741016603336339668480713086597214599300426576425196211452997902266749341","seed":97486741016603336339668480713086597214599300426576425196211452997902266749341,"line":15583,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9987930633 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 9987930633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.43153466768237971919571226931864723320027823028734862923591825076747455572086","seed":43153466768237971919571226931864723320027823028734862923591825076747455572086,"line":2209,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2965287759 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2965287759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.107882766065075640242436031989071033331483049071218407324654590691971230467728","seed":107882766065075640242436031989071033331483049071218407324654590691971230467728,"line":196,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 500657024 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 500657024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"15.lc_ctrl_stress_all_with_rand_reset.16941588662592686371775109563737929097925281307613802709180384415504490659305","seed":16941588662592686371775109563737929097925281307613802709180384415504490659305,"line":4773,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16672782877 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16672782877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.16542129518484851648575161360906088138874799965851549153211560640020694400514","seed":16542129518484851648575161360906088138874799965851549153211560640020694400514,"line":4294,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16151532159 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16151532159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.114660094988424674533061892973444947527561734521625169670269052263140767287707","seed":114660094988424674533061892973444947527561734521625169670269052263140767287707,"line":207,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 796205236 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 796205236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.26739969971459354707481761904286560414561770403859703306674276258370774661911","seed":26739969971459354707481761904286560414561770403859703306674276258370774661911,"line":11004,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3162325797 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3162325797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.31454481313819487038565412073874054467458685729429027958633360417130375494945","seed":31454481313819487038565412073874054467458685729429027958633360417130375494945,"line":4900,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4544476626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4544476626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.103649258461840369180244382992456373325054751991955589321716386905919210387468","seed":103649258461840369180244382992456373325054751991955589321716386905919210387468,"line":3117,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6424471524 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6424471524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.84873969590174727623857896032195395635029042166363552400716658799036605509692","seed":84873969590174727623857896032195395635029042166363552400716658799036605509692,"line":1062,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2645671089 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2645671089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.80863105061029508145271039927136893788952555679949312696851643955341339799969","seed":80863105061029508145271039927136893788952555679949312696851643955341339799969,"line":5242,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7344679049 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7344679049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.54975361918991542677362139909067557205171313711938735422383908577544985913523","seed":54975361918991542677362139909067557205171313711938735422383908577544985913523,"line":163,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4277361263 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4277361263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.75044589776115220137512534007825342340496834213144413780863277025799215819164","seed":75044589776115220137512534007825342340496834213144413780863277025799215819164,"line":166,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1114552022 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1114552022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.48074988000085117643417949394244355924585162559433712516140292849342247150810","seed":48074988000085117643417949394244355924585162559433712516140292849342247150810,"line":4783,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1836680527 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1836680527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.10972879421295357469589101664177105593482624242963621173054596645745518554212","seed":10972879421295357469589101664177105593482624242963621173054596645745518554212,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 108986018 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 108986018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.98255533378700176376397079235407795013349876123331735830941019360250436336898","seed":98255533378700176376397079235407795013349876123331735830941019360250436336898,"line":4078,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3394688261 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3394688261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!":[{"name":"lc_ctrl_jtag_priority","qual_name":"6.lc_ctrl_jtag_priority.87071407361614406638289392153482540776039897574240729782499309643012652989272","seed":87071407361614406638289392153482540776039897574240729782499309643012652989272,"line":148,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest/run.log","log_context":["UVM_FATAL @ 10003121910 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!\n","UVM_INFO @ 10003121910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2003,"total":2035,"percent":98.42751842751842}