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---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.48928396819199048815375376307058899901184397782271808562419910645900837541682","seed":48928396819199048815375376307058899901184397782271808562419910645900837541682,"line":175,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 945154602 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 945154602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.53784864457613802304839231572667514956339641688286372178479172042849553436347","seed":53784864457613802304839231572667514956339641688286372178479172042849553436347,"line":168,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 307726994 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 307726994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_zero_state_err_urnd","qual_name":"1.otbn_zero_state_err_urnd.21129004404458308138720999375026115328841733797226204665022531638512246077708","seed":21129004404458308138720999375026115328841733797226204665022531638512246077708,"line":105,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9600746 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","UVM_ERROR @   9600746 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @   9600746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_stack_addr_integ_chk","qual_name":"4.otbn_stack_addr_integ_chk.51186403442156497825749574361186471368615051574191854759800230082415271467806","seed":51186403442156497825749574361186471368615051574191854759800230082415271467806,"line":117,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32531798 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 32531798 PS) Assertion tb.model_if.NoModelErrs has failed \n","UVM_ERROR @  32531798 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  32531798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)":[{"name":"otbn_partial_wipe","qual_name":"2.otbn_partial_wipe.111658666713239719314329038916428474247562164725564855748272047097356045660353","seed":111658666713239719314329038916428474247562164725564855748272047097356045660353,"line":118,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,161): (time 10898730 PS) Assertion tb.dut.idle_checker.IdleIfLockedAndNotRotatingKeys_A has failed (3 cycles, starting 10846098 PS)\n","UVM_ERROR @  10898730 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A\n","UVM_INFO @  10898730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status":[{"name":"otbn_partial_wipe","qual_name":"4.otbn_partial_wipe.6010197530986800888643492682443029511062126774265891216676389551299783042536","seed":6010197530986800888643492682443029511062126774265891216676389551299783042536,"line":114,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log","log_context":["UVM_ERROR @   7061294 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status\n","UVM_INFO @   7061294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.":[{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"10.otbn_passthru_mem_tl_intg_err.49377692421295586146309699156798130254797287486448069782427190603026651616173","seed":49377692421295586146309699156798130254797287486448069782427190603026651616173,"line":86,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/10.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  23269265 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.\n","UVM_INFO @  23269265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.":[{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"19.otbn_passthru_mem_tl_intg_err.33971179071323090000702043283262474591770899996415995251849292987764516045854","seed":33971179071323090000702043283262474591770899996415995251849292987764516045854,"line":86,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/19.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  10214892 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.\n","UVM_INFO @  10214892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1851,"total":1867,"percent":99.14301017675415}