{"block":{"name":"spi_device","variant":"1r1w","commit":"34fa6f9bc35e15dc92c9ad207268e94b88162789","commit_short":"34fa6f9","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789","revision_info":"GitHub Revision: [`34fa6f9`](https://github.com/lowrisc/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-29T00:12:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":611.44,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.89,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":33.29,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":19.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":4.25,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.89,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":19.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":1.05,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":2.12,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":140,"total":140,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.21,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.07,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":0.89,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":6.59,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":6.59,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":25.12,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.53,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":43.02,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":32.01,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":34.35,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":34.35,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":30.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":30.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":30.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":30.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":30.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":25.11,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":131.61,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":131.61,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":131.61,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":56.99,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":14.38,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":131.61,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":512.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":26.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":26.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":611.44,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":472.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":762.26,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":4.93,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":4.93,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":2.89,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":19.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":5.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.8,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":2.89,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":19.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":5.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":2139,"total":2161,"percent":98.9819527996298},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.73,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":16.83,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":16.83,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":45,"total":45,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":312.66,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"coverage":{"code":{"block":null,"line_statement":99.1,"branch":98.4,"condition_expression":96.56,"toggle":83.54,"fsm":89.36},"assertion":94.76,"functional":99.26},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.64412688334331992197901727177628466449082551063975335990288438421770515074779","seed":64412688334331992197901727177628466449082551063975335990288438421770515074779,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1175053 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[38])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1175053 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1175053 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[934])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.45891045188858485438451461241121980466398639878518319001007216166332149912654","seed":45891045188858485438451461241121980466398639878518319001007216166332149912654,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1841239 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[104])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1841239 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1841239 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.36791130954846298277805863390011094177266302612374595715526088073132889163231","seed":36791130954846298277805863390011094177266302612374595715526088073132889163231,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4774039 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[60])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4774039 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4774039 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.67505212745285644370742327146210370312065292691545863282143317911147840288255","seed":67505212745285644370742327146210370312065292691545863282143317911147840288255,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   2459104 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[60])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2459104 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2459104 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.93555461106652803165542402461362780038693078672115351797898338263558533098116","seed":93555461106652803165542402461362780038693078672115351797898338263558533098116,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @  10984173 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[12])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  10984173 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  10984173 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[908])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.93011666618220447535893474533499291613940641348644520545510015473516176322123","seed":93011666618220447535893474533499291613940641348644520545510015473516176322123,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4179885 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[30])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4179885 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4179885 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[926])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.41056704545011684733532053701382765911888724515521280858422206676353684835773","seed":41056704545011684733532053701382765911888724515521280858422206676353684835773,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4316594 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[45])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4316594 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4316594 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[941])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.15169147577287218724409819959530841920635194029010723232861828457848527149975","seed":15169147577287218724409819959530841920635194029010723232861828457848527149975,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1558345 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1558345 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1558345 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.53959349517588517490013079388338987955880474766343869875952981370144436608657","seed":53959349517588517490013079388338987955880474766343869875952981370144436608657,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1680110 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[36])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1680110 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1680110 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[932])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.71754987522078009474136901663362387882000502271669143245158169509672311399217","seed":71754987522078009474136901663362387882000502271669143245158169509672311399217,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @    930206 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    930206 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    930206 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.34742549089120190356653872323990794406417896402973841340598842221606344093677","seed":34742549089120190356653872323990794406417896402973841340598842221606344093677,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1618269 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[84])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1618269 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1618269 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.104740254636734785040972136150687969896247620724743546331229870713755647468542","seed":104740254636734785040972136150687969896247620724743546331229870713755647468542,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1307675 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1307675 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1307675 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.114874659037022322423116861590303448255520926218345821798578829435374490440937","seed":114874659037022322423116861590303448255520926218345821798578829435374490440937,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4055385 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[42])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4055385 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4055385 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.10568780225647590267214719487017209277117863524927653939985434301067974258955","seed":10568780225647590267214719487017209277117863524927653939985434301067974258955,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   7250538 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[8])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   7250538 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   7250538 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.87434486039135260910270435757272216294404420853889206292445295935990565011178","seed":87434486039135260910270435757272216294404420853889206292445295935990565011178,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   3799419 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[43])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3799419 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3799419 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.73939282107854455484865435544755129774717481899223804308766441173174376489795","seed":73939282107854455484865435544755129774717481899223804308766441173174376489795,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1650891 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[35])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1650891 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1650891 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.58640822663624316809630855052409903425451729387910823027830315521922802167116","seed":58640822663624316809630855052409903425451729387910823027830315521922802167116,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @    927267 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    927267 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    927267 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.22162935250854855421423737023260793590421843761087714711084140495842971930411","seed":22162935250854855421423737023260793590421843761087714711084140495842971930411,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   5913538 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[98])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5913538 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5913538 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.104910507579080999538822021790649174807223972322695831702716430701480736109055","seed":104910507579080999538822021790649174807223972322695831702716430701480736109055,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   2142753 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[56])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2142753 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2142753 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[952])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.4447980789573966645050109095218976909592076820657671536396925743989344358012","seed":4447980789573966645050109095218976909592076820657671536396925743989344358012,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1079023 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[21])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1079023 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1079023 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.34155398983402899509846759128908677461869124996203691134229518533398489879241","seed":34155398983402899509846759128908677461869124996203691134229518533398489879241,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1388172 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd208a5 [110100100000100010100101] vs 0x0 [0]) \n","UVM_ERROR @   1400172 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xef6fd7 [111011110110111111010111] vs 0x0 [0]) \n","UVM_ERROR @   1495172 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c771e [111000111011100011110] vs 0x0 [0]) \n","UVM_ERROR @   1544172 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x182a9a [110000010101010011010] vs 0x0 [0]) \n","UVM_ERROR @   1567172 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd8b27d [110110001011001001111101] vs 0x0 [0]) \n"]}],"Job timed out after * minutes":[{"name":"spi_device_flash_mode_ignore_cmds","qual_name":"15.spi_device_flash_mode_ignore_cmds.48996859877363581888067030751503233676649131324423061995482287455091049664162","seed":48996859877363581888067030751503233676649131324423061995482287455091049664162,"line":null,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest/run.log","log_context":["Job timed out after 60 minutes"]}],"UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *":[{"name":"spi_device_flash_mode_ignore_cmds","qual_name":"27.spi_device_flash_mode_ignore_cmds.91853256563035826985379729690595035513976386355599934857089797244887548235364","seed":91853256563035826985379729690595035513976386355599934857089797244887548235364,"line":79,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest/run.log","log_context":["UVM_ERROR @ 499987814 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0\n","UVM_INFO @ 867866426 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/12\n","UVM_INFO @ 867866426 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/12\n","tl_ul_fuzzy_flash_status_q[i] = 0xe7ddf0\n","tl_ul_fuzzy_flash_status_q[i] = 0xe7ddf0\n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_stress_all","qual_name":"38.spi_device_stress_all.106345614384407250464355389529994669777626459457361146757068809956059654671508","seed":106345614384407250464355389529994669777626459457361146757068809956059654671508,"line":121,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest/run.log","log_context":["UVM_ERROR @ 14733011970 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10800128 [0xa4cc00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xa4cc00 != exp 0x0\n","UVM_INFO @ 15826603279 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/12\n","UVM_INFO @ 15826603279 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 8/12\n","tl_ul_fuzzy_flash_status_q[i] = 0x673a88\n","tl_ul_fuzzy_flash_status_q[i] = 0xdbbe94\n"]}]}},"passed":2372,"total":2396,"percent":98.9983305509182}