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---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.33434372671623169836193206316707674211458787671546480577407985291478572496914","seed":33434372671623169836193206316707674211458787671546480577407985291478572496914,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   2398213 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   2398213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp 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---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"12.sram_ctrl_readback_err.22586869602692090165909496085232430693034172397746210040268840758160566485383","seed":22586869602692090165909496085232430693034172397746210040268840758160566485383,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 1568385329 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x13)\n","UVM_INFO @ 1568385329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary 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---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"23.sram_ctrl_readback_err.80163033339345158052073757714925595426466398241160504180688076046128012568385","seed":80163033339345158052073757714925595426466398241160504180688076046128012568385,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/23.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 2745365132 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x17)\n","UVM_INFO @ 2745365132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"26.sram_ctrl_readback_err.4960763982850220333776139784088955880635767970855758068993656406425379823299","seed":4960763982850220333776139784088955880635767970855758068993656406425379823299,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/26.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 707694734 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x21) != exp (0x4c)\n","UVM_INFO @ 707694734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"31.sram_ctrl_readback_err.87821363086089990900489050502852168065966541108756709639405766778285625128414","seed":87821363086089990900489050502852168065966541108756709639405766778285625128414,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/31.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 685254545 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x15)\n","UVM_INFO @ 685254545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"32.sram_ctrl_readback_err.87889797434064190720522864351055038592980681755076931344992543380479944642450","seed":87889797434064190720522864351055038592980681755076931344992543380479944642450,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/32.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 2641361849 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x15)\n","UVM_INFO @ 2641361849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"39.sram_ctrl_readback_err.5207133886181251252158546068997030079632942598524934201799046613193548376027","seed":5207133886181251252158546068997030079632942598524934201799046613193548376027,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/39.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 722959104 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x4a)\n","UVM_INFO @ 722959104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"49.sram_ctrl_readback_err.56312712673918599804674736810505097527136818569159750707575656517381291543442","seed":56312712673918599804674736810505097527136818569159750707575656517381291543442,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/49.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 686688155 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x5b)\n","UVM_INFO @ 686688155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"7.sram_ctrl_mubi_enc_err.50858936123315211502220097761455939872251356038680868037037800433100945128746","seed":50858936123315211502220097761455939872251356038680868037037800433100945128746,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 3463714346 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 3463714346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"9.sram_ctrl_mubi_enc_err.14503725764072787216327902559976079085106132869093550053648207004530488717046","seed":14503725764072787216327902559976079085106132869093550053648207004530488717046,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 5051107738 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 5051107738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"11.sram_ctrl_mubi_enc_err.51002518489042418273723164505520645578055212539737071007887828091726372453241","seed":51002518489042418273723164505520645578055212539737071007887828091726372453241,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 3086948434 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 3086948434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"16.sram_ctrl_mubi_enc_err.115364857561147446266004360700114670483344297720278007441335003906581724527681","seed":115364857561147446266004360700114670483344297720278007441335003906581724527681,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 658163045 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 658163045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"21.sram_ctrl_mubi_enc_err.21730079392576551916780778521104915733113557680849009865243465494292278822586","seed":21730079392576551916780778521104915733113557680849009865243465494292278822586,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/21.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 684719152 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 684719152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"26.sram_ctrl_mubi_enc_err.45208783468893948655278187777364596721044282685111783688725710195101852433443","seed":45208783468893948655278187777364596721044282685111783688725710195101852433443,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/26.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 1050245882 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 1050245882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"33.sram_ctrl_mubi_enc_err.4502097085317924059682126559674446490485345230126413292366585922065579843505","seed":4502097085317924059682126559674446490485345230126413292366585922065579843505,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/33.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 3287735977 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 3287735977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"41.sram_ctrl_mubi_enc_err.2457757597722109778550750618441920271083497235052809188032269765791888255822","seed":2457757597722109778550750618441920271083497235052809188032269765791888255822,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/41.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 1278706609 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 1278706609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"sram_ctrl_bijection","qual_name":"12.sram_ctrl_bijection.97697631763815168319742627210980362315314142560323637419951945243250590909712","seed":97697631763815168319742627210980362315314142560323637419951945243250590909712,"line":96,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest/run.log","log_context":["UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"sram_ctrl_readback_err","qual_name":"16.sram_ctrl_readback_err.65751673021462182487259721406093400289594818311878004059094858173339517019662","seed":65751673021462182487259721406093400289594818311878004059094858173339517019662,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/16.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 1380853089 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).\n"," TL item was: req: (cip_tl_seq_item@6033) { a_addr: 'h567ebc48  a_data: 'h7b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h1  a_user: 'h26ef6  d_param: 'h0  d_source: 'h28  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @ 1380853089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}]}},"passed":1898,"total":1950,"percent":97.33333333333333}