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---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"6.sram_ctrl_mubi_enc_err.100205632941709456245828302094034884780085360270167788416488055671538734813444","seed":100205632941709456245828302094034884780085360270167788416488055671538734813444,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  64131948 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  64131948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"21.sram_ctrl_mubi_enc_err.113104228406329319460667715279205460404481531345006203964101212926664183031368","seed":113104228406329319460667715279205460404481531345006203964101212926664183031368,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 118403462 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 118403462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"22.sram_ctrl_mubi_enc_err.13984835500595933446552551209926238310644574318892515595566063275586001930365","seed":13984835500595933446552551209926238310644574318892515595566063275586001930365,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  86812136 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  86812136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"44.sram_ctrl_mubi_enc_err.75931422520143287871426734217469804195620017728757129301805706569526009969126","seed":75931422520143287871426734217469804195620017728757129301805706569526009969126,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  66566271 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  66566271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.60299507987390226679656338202379118966892041319632003787045709435875511791368","seed":60299507987390226679656338202379118966892041319632003787045709435875511791368,"line":103,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   9212797 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   9212797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.99262874110288199360409615239674435008197720265856249623833758545898961809248","seed":99262874110288199360409615239674435008197720265856249623833758545898961809248,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   3267314 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   3267314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$isunknown(rdata_o))'":[{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.10640624887461937997245468308642624647229653238884984061382350404508258808648","seed":10640624887461937997245468308642624647229653238884984061382350404508258808648,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @   5968144 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @   5968144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"3.sram_ctrl_readback_err.17939588909881380408785326578788169591092394239934579161509774888469527461991","seed":17939588909881380408785326578788169591092394239934579161509774888469527461991,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  86650974 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x5c)\n","UVM_INFO @  86650974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"5.sram_ctrl_readback_err.90112857675522675522183145025322663104196187296099161389998809228306215462957","seed":90112857675522675522183145025322663104196187296099161389998809228306215462957,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  51604369 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x55)\n","UVM_INFO @  51604369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"8.sram_ctrl_readback_err.29704524446489336472321178420911285026322426815495436920844893406240031150987","seed":29704524446489336472321178420911285026322426815495436920844893406240031150987,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  27255499 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0xe)\n","UVM_INFO @  27255499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"11.sram_ctrl_readback_err.108418216945531422980078881139987439387136543072619366602299422402200377560365","seed":108418216945531422980078881139987439387136543072619366602299422402200377560365,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  51057926 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x48)\n","UVM_INFO @  51057926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"17.sram_ctrl_readback_err.80489118665348671013412197391308990994967025667748236334752057951603824064105","seed":80489118665348671013412197391308990994967025667748236334752057951603824064105,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  29277800 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x4e)\n","UVM_INFO @  29277800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"19.sram_ctrl_readback_err.7288789862415978343357630027660265293037277112479002653633914046520316914990","seed":7288789862415978343357630027660265293037277112479002653633914046520316914990,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  27798641 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5e) != exp (0x55)\n","UVM_INFO @  27798641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"21.sram_ctrl_readback_err.81216961633610399822323138035546956676469348655871310477957948972816822047436","seed":81216961633610399822323138035546956676469348655871310477957948972816822047436,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/21.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  68536097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x11) != exp (0x38)\n","UVM_INFO @  68536097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"26.sram_ctrl_readback_err.38146332486638248497703462238379776401269841090327659462809547408017526677229","seed":38146332486638248497703462238379776401269841090327659462809547408017526677229,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/26.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 115577774 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x16)\n","UVM_INFO @ 115577774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"28.sram_ctrl_readback_err.82172291413789941249030962852315870355047461154669488625340589298967868024513","seed":82172291413789941249030962852315870355047461154669488625340589298967868024513,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/28.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  92268647 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x20)\n","UVM_INFO @  92268647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"33.sram_ctrl_readback_err.68510750312709871520980447747884958645587218995033947864376452429811523653977","seed":68510750312709871520980447747884958645587218995033947864376452429811523653977,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/33.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  90970137 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x27)\n","UVM_INFO @  90970137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"36.sram_ctrl_readback_err.96206184303233822160072595974196970471164003562234645542897454429229516407277","seed":96206184303233822160072595974196970471164003562234645542897454429229516407277,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/36.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 395113174 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x3f)\n","UVM_INFO @ 395113174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"37.sram_ctrl_readback_err.54482317485944774371350738187791233102308266328390673029816487715578611889356","seed":54482317485944774371350738187791233102308266328390673029816487715578611889356,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/37.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 269629551 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x76)\n","UVM_INFO @ 269629551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"41.sram_ctrl_readback_err.12777828082105372129539815047541715253609841164963663615245179313241894658658","seed":12777828082105372129539815047541715253609841164963663615245179313241894658658,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/41.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  38302775 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x63) != exp (0x13)\n","UVM_INFO @  38302775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"43.sram_ctrl_readback_err.104821450791066243799755975795984471310279723396327826623279473742121039908383","seed":104821450791066243799755975795984471310279723396327826623279473742121039908383,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/43.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  29998938 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x69)\n","UVM_INFO @  29998938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'":[{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.92767407290655295071041493498704062655436855815671443890005184925445447267591","seed":92767407290655295071041493498704062655436855815671443890005184925445447267591,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1526854ps failed at 1526854ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 1537271ps failed at 1537271ps\n","\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.36543984085002586122397035571128424495256292831978634383288002247653843141392","seed":36543984085002586122397035571128424495256292831978634383288002247653843141392,"line":101,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3469843ps failed at 3469843ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","UVM_ERROR @   6615702 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   6615702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire":[{"name":"sram_ctrl_readback_err","qual_name":"34.sram_ctrl_readback_err.75289876952814667394921121827795167459098059496049171173076608110291222745040","seed":75289876952814667394921121827795167459098059496049171173076608110291222745040,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/34.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  27093044 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire\n","UVM_INFO @  27093044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1899,"total":1950,"percent":97.38461538461539}