{"block":{"name":"sysrst_ctrl","variant":null,"commit":"34fa6f9bc35e15dc92c9ad207268e94b88162789","commit_short":"34fa6f9","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789","revision_info":"GitHub Revision: [`34fa6f9`](https://github.com/lowrisc/opentitan/tree/34fa6f9bc35e15dc92c9ad207268e94b88162789)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-29T00:12:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":8.39,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":10.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":6.08,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":5.06,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":9.75,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":200.91,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":9.71,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":5.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.71,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":190,"total":190,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":388.87,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":239.34,"sim_time":0.0,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":515.63,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":12.36,"sim_time":0.0,"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":9.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":1537.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":10.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":439.41,"sim_time":0.0,"passed":42,"total":50,"percent":84.0}},"passed":42,"total":50,"percent":84.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":111.75,"sim_time":0.0,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":405.73,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.92,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":6.29,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":6.62,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":6.62,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":9.75,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.71,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":29.53,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":9.75,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.27,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.71,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":29.53,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":775,"total":792,"percent":97.85353535353535},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":109.46,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":90.94,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":90.94,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":45,"total":45,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":22.02,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"coverage":{"code":{"block":null,"line_statement":98.88,"branch":99.0,"condition_expression":97.93,"toggle":100.0,"fsm":93.59},"assertion":98.08,"functional":87.75},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"1.sysrst_ctrl_stress_all_with_rand_reset.10034389715466849771836633936821360050679593321432550204001458388152298114128","seed":10034389715466849771836633936821360050679593321432550204001458388152298114128,"line":699,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 18604825819 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 18604931083 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 18604931083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"2.sysrst_ctrl_edge_detect.48127942592508012738132780642721490736221300736966837051463779198638543656985","seed":48127942592508012738132780642721490736221300736966837051463779198638543656985,"line":665,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3711100665 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 3711143219 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3711143219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"5.sysrst_ctrl_edge_detect.58151034147464218077486240043581480212728826996161955456795574907931073380687","seed":58151034147464218077486240043581480212728826996161955456795574907931073380687,"line":664,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4315615069 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4315635477 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4315635477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"9.sysrst_ctrl_edge_detect.78071837200160422643856335349530865374865305718814271178449982686171143035956","seed":78071837200160422643856335349530865374865305718814271178449982686171143035956,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4597001427 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4597012137 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4597012137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"37.sysrst_ctrl_ultra_low_pwr.44057299572125822193609435037685709339229193904133672153629907227375207808964","seed":44057299572125822193609435037685709339229193904133672153629907227375207808964,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 234504556181 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 234504597847 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 234504597847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"44.sysrst_ctrl_ultra_low_pwr.12931019722708825847315227615432517641570674824350247188908455491925359750131","seed":12931019722708825847315227615432517641570674824350247188908455491925359750131,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4552120965 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4552254299 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4552254299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"48.sysrst_ctrl_ultra_low_pwr.94545891451017674905699749147933614804876986406525136143493426786520729303762","seed":94545891451017674905699749147933614804876986406525136143493426786520729303762,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4913727491 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_ERROR @ 4913768307 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4913768307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"3.sysrst_ctrl_ultra_low_pwr.106046964319001082812753005226604403535198856995997739592909859892983826593469","seed":106046964319001082812753005226604403535198856995997739592909859892983826593469,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5797567501 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_ERROR @ 6330067501 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 6330067501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"11.sysrst_ctrl_ultra_low_pwr.43615998826900461826571350152024190397519417962028544164968976507213150133450","seed":43615998826900461826571350152024190397519417962028544164968976507213150133450,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 394908966997 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 395306466997 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 866261466997 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 866276739100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"19.sysrst_ctrl_ultra_low_pwr.1828208535087516737090006397587891793926533512897920916120827711571236792010","seed":1828208535087516737090006397587891793926533512897920916120827711571236792010,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2343638180 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 2461138180 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 3331138180 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 4801262707 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 4815341395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"26.sysrst_ctrl_ultra_low_pwr.33335153347758179882232112283112853082656407059855360249401625768974251662527","seed":33335153347758179882232112283112853082656407059855360249401625768974251662527,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2275082253 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 2282582253 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 3867582253 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 3880209116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"41.sysrst_ctrl_ultra_low_pwr.103507433543226966948054788216321424673210773562259356129310732179308128990080","seed":103507433543226966948054788216321424673210773562259356129310732179308128990080,"line":650,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2100565391 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_INFO @ 2338065391 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 3438065391 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 6783065391 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 6810837336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"42.sysrst_ctrl_stress_all_with_rand_reset.12035901105885836613423341546472231302490905460710623052335117357984930169110","seed":12035901105885836613423341546472231302490905460710623052335117357984930169110,"line":685,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15856317377 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    \u0001 \n","UVM_ERROR @ 16763817377 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 16763817377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"10.sysrst_ctrl_combo_detect_with_pre_cond.21897677569630166003595548017414152024887213112020298322666032085627761848869","seed":21897677569630166003595548017414152024887213112020298322666032085627761848869,"line":688,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 38937523616 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_ERROR @ 38937523616 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 38937523616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"22.sysrst_ctrl_combo_detect_with_pre_cond.79411277130431753686801781180800877164543260279468585730819058411288350850914","seed":79411277130431753686801781180800877164543260279468585730819058411288350850914,"line":713,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 73276693665 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_ERROR @ 73276693665 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 73276693665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"61.sysrst_ctrl_combo_detect_with_pre_cond.82127006084519657668859837216118560782521283915644320849658886231935061804513","seed":82127006084519657668859837216118560782521283915644320849658886231935061804513,"line":760,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 94106238767 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 94241238767 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 94261238767 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 104404251250 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e\n","UVM_INFO @ 104404394108 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x12\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"15.sysrst_ctrl_combo_detect_with_pre_cond.56795357909577717937109281368310995940152425770275581163548559610584686559390","seed":56795357909577717937109281368310995940152425770275581163548559610584686559390,"line":721,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 83851118679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (4 [0x4] vs 6 [0x6]) \n","UVM_INFO @ 93962718679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30\n","UVM_INFO @ 93962798679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25\n","UVM_INFO @ 94346198679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1\n","UVM_INFO @ 94361028267 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= e\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"69.sysrst_ctrl_combo_detect_with_pre_cond.68614840453857124265448301969495833305586492301597164838452687446399280898614","seed":68614840453857124265448301969495833305586492301597164838452687446399280898614,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 14968102780 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4 \n","UVM_ERROR @ 14968102780 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4 \n","UVM_INFO @ 14968102780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"75.sysrst_ctrl_combo_detect_with_pre_cond.28883713932648043392373322686655769406248983506080830373294986038090234014636","seed":28883713932648043392373322686655769406248983506080830373294986038090234014636,"line":692,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 44611381155 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_ERROR @ 44611381155 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 44611381155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":1058,"total":1077,"percent":98.23584029712164}