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[`5ec693e`](https://github.com/lowrisc/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-05T00:07:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":1.57,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.24,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":14.32,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.66,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":2.18,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.66,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":130,"total":130,"percent":100.0},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":1.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"extclk":{"tests":{"clkmgr_extclk":{"max_time":1.41,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.28,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":1.57,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":13.69,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":12.32,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":13.69,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":56.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":3.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":3.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.24,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.66,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.99,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.24,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.66,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.99,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":640,"total":640,"percent":100.0},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":2.87,"sim_time":0.0,"passed":2,"total":5,"percent":40.0},"clkmgr_tl_intg_err":{"max_time":2.98,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":22,"total":25,"percent":88.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.51,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.51,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.51,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.51,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":4.41,"sim_time":0.0,"passed":16,"total":20,"percent":80.0}},"passed":16,"total":20,"percent":80.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":2.98,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":13.69,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":12.32,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.51,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":1.6,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_ctrl_intersig_mubi":{"tests":{"clkmgr_lc_ctrl_intersig_mubi":{"max_time":1.56,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_ctrl_clk_handshake_intersig_mubi":{"tests":{"clkmgr_lc_clk_byp_req_intersig_mubi":{"max_time":1.5,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_clk_handshake_intersig_mubi":{"tests":{"clkmgr_clk_handshake_intersig_mubi":{"max_time":1.59,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sec_cm_div_intersig_mubi":{"tests":{"clkmgr_div_intersig_mubi":{"max_time":1.71,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":2.87,"sim_time":0.0,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.26,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":2.87,"sim_time":0.0,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0}},"passed":570,"total":585,"percent":97.43589743589743},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":7.32,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":153.88,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0}},"passed":99,"total":100,"percent":99.0}},"coverage":{"code":{"block":null,"line_statement":99.38,"branch":99.26,"condition_expression":96.31,"toggle":100.0,"fsm":100.0},"assertion":96.47,"functional":87.82},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.76321990772338938611162562928334040917351475516611803660258777926393915380523","seed":76321990772338938611162562928334040917351475516611803660258777926393915380523,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6425010 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @   6425010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"1.clkmgr_sec_cm.10835823920366785697415407460963875930055882834651406320341528693343319226846","seed":10835823920366785697415407460963875930055882834651406320341528693343319226846,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @   8350054 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @   8350054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"3.clkmgr_sec_cm.2822467397839654477067940323947476945710708479395581838520437490482187709597","seed":2822467397839654477067940323947476945710708479395581838520437490482187709597,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @   2169431 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @   2169431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'":[{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.53410748043735792155288982148613748595068366109583930420747519795336238640323","seed":53410748043735792155288982148613748595068366109583930420747519795336238640323,"line":305,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["\tOffending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'\n","UVM_ERROR @ 4220059845 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A\n","UVM_INFO @ 4220059845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch":[{"name":"clkmgr_clk_handshake_intersig_mubi","qual_name":"27.clkmgr_clk_handshake_intersig_mubi.93210599209391042455423781232745961092770229854818528747890577376721703976818","seed":93210599209391042455423781232745961092770229854818528747890577376721703976818,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest/run.log","log_context":["UVM_ERROR @   7085626 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (13 [0xd] vs 9 [0x9]) extclk_status mismatch\n","UVM_INFO @   7085626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_clk_handshake_intersig_mubi","qual_name":"38.clkmgr_clk_handshake_intersig_mubi.72910075178801979621310478108800186658875141313032596609647643347411719514629","seed":72910075178801979621310478108800186658875141313032596609647643347411719514629,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest/run.log","log_context":["UVM_ERROR @   6391302 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (5 [0x5] vs 9 [0x9]) extclk_status mismatch\n","UVM_INFO @   6391302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.38468065248147737417314536313093621347475352339186686020961592757617479546092","seed":38468065248147737417314536313093621347475352339186686020961592757617479546092,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  57540140 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: 0x0  Write_and_check_update_error task: check storage_err status\n","UVM_INFO @  57540140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.22336530880067339904147983378231718813209981829862246042596308882133819083151","seed":22336530880067339904147983378231718813209981829862246042596308882133819083151,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  51585403 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!\n","UVM_INFO @  51585403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.115426399068557167376357395481808130371471933457850787701302860497636873457745","seed":115426399068557167376357395481808130371471933457850787701302860497636873457745,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 167088015 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!\n","UVM_INFO @ 167088015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.72649805551015424118941230836397917252615982156063439155827525016247765504780","seed":72649805551015424118941230836397917252615982156063439155827525016247765504780,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  85146325 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!\n","UVM_INFO @  85146325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1439,"total":1455,"percent":98.90034364261169}