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---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"11.edn_stress_all_with_rand_reset.78152587447441877265112639767714380528347931137288137583181968348858182713786","seed":78152587447441877265112639767714380528347931137288137583181968348858182713786,"line":110,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/11.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 120458910 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 120458910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"15.edn_stress_all_with_rand_reset.86892924155755693479856453723441781607928189146331135565835254977245055765075","seed":86892924155755693479856453723441781607928189146331135565835254977245055765075,"line":294,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2645567602 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2645567602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"21.edn_stress_all_with_rand_reset.109584469570536915398608667189811653575923929412714441908839626149006040207126","seed":109584469570536915398608667189811653575923929412714441908839626149006040207126,"line":301,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1335084476 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1335084476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"27.edn_stress_all_with_rand_reset.14040688741778903275975772377203119922335566925691886721292663668342820082685","seed":14040688741778903275975772377203119922335566925691886721292663668342820082685,"line":201,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1363426247 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1363426247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"45.edn_stress_all_with_rand_reset.35406441720457422935281581144626406639815642747189117984005405428637814545265","seed":35406441720457422935281581144626406639815642747189117984005405428637814545265,"line":195,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/45.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2347382344 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2347382344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"14.edn_disable_auto_req_mode.72670994141450508948571306554734843267681757667681998993608142030796074001946","seed":72670994141450508948571306554734843267681757667681998993608142030796074001946,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"19.edn_disable_auto_req_mode.64847882304463544346211485255138710072854914827162631136410058985355116187684","seed":64847882304463544346211485255138710072854914827162631136410058985355116187684,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"22.edn_disable_auto_req_mode.50294949404026901429031613489564864283047234882755088126339195850116187192916","seed":50294949404026901429031613489564864283047234882755088126339195850116187192916,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.74598659501244536421283769656407946910484758490039562424330776640701822973954","seed":74598659501244536421283769656407946910484758490039562424330776640701822973954,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"39.edn_disable_auto_req_mode.40603882137180649854156287662931834447657928111695581960531118566248262576777","seed":40603882137180649854156287662931834447657928111695581960531118566248262576777,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/39.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"16.edn_disable_auto_req_mode.54518647625351297488059798070491803727815965075425825965400174679069792397999","seed":54518647625351297488059798070491803727815965075425825965400174679069792397999,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/16.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  21462217 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00c7e642 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  21462217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"20.edn_disable_auto_req_mode.15059113273222174346182616164838430107780052689232020468818968705409996541838","seed":15059113273222174346182616164838430107780052689232020468818968705409996541838,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/20.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  10410796 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003f2912 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  10410796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"25.edn_disable_auto_req_mode.52936126777570013637847674561182068528100783437984775101816211673872150891374","seed":52936126777570013637847674561182068528100783437984775101816211673872150891374,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/25.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  56684813 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0044d642 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  56684813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2486,"total":2500,"percent":99.44}