{"block":{"name":"edn","variant":"edn1","commit":"5ec693e5db09b2eb99805c3547847c68e0be36bf","commit_short":"5ec693e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf","revision_info":"GitHub Revision: [`5ec693e`](https://github.com/lowrisc/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-05T00:07:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn1/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.36,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":0.96,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":0.95,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":3.85,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.25,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":1.49,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":0.95,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.25,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":130,"total":130,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":187.4,"sim_time":0.0,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":187.4,"sim_time":0.0,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":187.4,"sim_time":0.0,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.57,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.57,"sim_time":0.0,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.52,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":9.42,"sim_time":0.0,"passed":44,"total":50,"percent":88.0}},"passed":94,"total":100,"percent":94.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":5.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":0.84,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":1.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":2.83,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":2.83,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.96,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.95,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.25,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.09,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.96,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.95,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.25,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.09,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1634,"total":1640,"percent":99.63414634146342},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"edn_tl_intg_err":{"max_time":3.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":1.35,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.57,"sim_time":0.0,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.57,"sim_time":0.0,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":4.98,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.57,"sim_time":0.0,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":3.44,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":680,"total":680,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":90.06,"sim_time":0.0,"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0}},"coverage":{"code":{"block":null,"line_statement":98.48,"branch":94.59,"condition_expression":95.08,"toggle":96.15,"fsm":97.73},"assertion":97.14,"functional":92.44},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"2.edn_stress_all_with_rand_reset.80252764464002690182002024347936894047623568136889986944613690690942538509737","seed":80252764464002690182002024347936894047623568136889986944613690690942538509737,"line":139,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 678009381 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 678009381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"6.edn_stress_all_with_rand_reset.12240105412925780999186272313985423747322714966844872458772399210231825565476","seed":12240105412925780999186272313985423747322714966844872458772399210231825565476,"line":290,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2623775557 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2623775557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"8.edn_stress_all_with_rand_reset.811455984606568125402878108144321750802551585801992001091833607525728355197","seed":811455984606568125402878108144321750802551585801992001091833607525728355197,"line":207,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1257132074 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1257132074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"18.edn_stress_all_with_rand_reset.44402758747193796497165236606407889124986393709419954775021897262704772999438","seed":44402758747193796497165236606407889124986393709419954775021897262704772999438,"line":162,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1240863982 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1240863982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.70686742930897393717408119211652546452555477487373591553214860536946005360665","seed":70686742930897393717408119211652546452555477487373591553214860536946005360665,"line":294,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3005592453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3005592453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"37.edn_stress_all_with_rand_reset.58511044757389631856582211749513133614053414147890966178978137773584905705150","seed":58511044757389631856582211749513133614053414147890966178978137773584905705150,"line":194,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2051480902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2051480902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"6.edn_disable_auto_req_mode.24354891728464805218584264216594829871175921432712254631532225665227401997105","seed":24354891728464805218584264216594829871175921432712254631532225665227401997105,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"41.edn_disable_auto_req_mode.113346138549891876288045352340702256786164402457747345573163308471637202316792","seed":113346138549891876288045352340702256786164402457747345573163308471637202316792,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/41.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"44.edn_disable_auto_req_mode.55119778902985454307606575618643652218549332164404269070882195943354041863886","seed":55119778902985454307606575618643652218549332164404269070882195943354041863886,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"46.edn_disable_auto_req_mode.8257289598410190925821482577559292330729383394468611786545642921058282238969","seed":8257289598410190925821482577559292330729383394468611786545642921058282238969,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"47.edn_disable_auto_req_mode.43858260127398057065372360475322617612971622126945264209910474766780276787234","seed":43858260127398057065372360475322617612971622126945264209910474766780276787234,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"37.edn_disable_auto_req_mode.98019067607290665767731831234381393845324390744378370350853680976503714318159","seed":98019067607290665767731831234381393845324390744378370350853680976503714318159,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  33160076 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f0e902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  33160076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2488,"total":2500,"percent":99.52}