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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"2.keymgr_stress_all_with_rand_reset.65145642679837769152622018770347284657982832710388514126641991198301763521814","seed":65145642679837769152622018770347284657982832710388514126641991198301763521814,"line":573,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 178963582 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 178963582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"4.keymgr_stress_all_with_rand_reset.25259733040257410009525308823555867577774918985812114380544800244040083021951","seed":25259733040257410009525308823555867577774918985812114380544800244040083021951,"line":297,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 243744042 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 243744042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"5.keymgr_stress_all_with_rand_reset.26395938426803665058280071139081303394830133071308313241628986187882081135178","seed":26395938426803665058280071139081303394830133071308313241628986187882081135178,"line":117,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 482007799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 482007799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.23570595176125410275468308785763880517480082146676950955555388089020213477142","seed":23570595176125410275468308785763880517480082146676950955555388089020213477142,"line":102,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 470128054 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 470128054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"10.keymgr_stress_all_with_rand_reset.14739290683819194401611114466415051080782417466367488304212169935184382122334","seed":14739290683819194401611114466415051080782417466367488304212169935184382122334,"line":1919,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1564397952 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1564397952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"12.keymgr_stress_all_with_rand_reset.66216421964216131333951525657652011122487396231666738550108717326762586998943","seed":66216421964216131333951525657652011122487396231666738550108717326762586998943,"line":484,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1125550306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1125550306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"13.keymgr_stress_all_with_rand_reset.67140843578159760186078741121487588252095697158287223366987114146917015255703","seed":67140843578159760186078741121487588252095697158287223366987114146917015255703,"line":360,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 703643758 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 703643758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"22.keymgr_stress_all_with_rand_reset.50077781306971534254910261674325435966225667207017774726573408232534891080672","seed":50077781306971534254910261674325435966225667207017774726573408232534891080672,"line":673,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 232380601 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 232380601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"25.keymgr_stress_all_with_rand_reset.56368429534147651641871724404229615640995772577683460566108968236916659528020","seed":56368429534147651641871724404229615640995772577683460566108968236916659528020,"line":97,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 220011005 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 220011005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"26.keymgr_stress_all_with_rand_reset.34067916302098139090668966662190556125556764650765041028582841004309455935665","seed":34067916302098139090668966662190556125556764650765041028582841004309455935665,"line":163,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 425137556 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 425137556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"28.keymgr_stress_all_with_rand_reset.34240588277936502607956153523151806530959457914036395210074435088828554384533","seed":34240588277936502607956153523151806530959457914036395210074435088828554384533,"line":756,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 807481610 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 807481610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"29.keymgr_stress_all_with_rand_reset.83676585086099423699015242644668793923171736927983636112646134505438986051943","seed":83676585086099423699015242644668793923171736927983636112646134505438986051943,"line":625,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 530163502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 530163502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.70214746752801856645732499541012355719033192755715539613510221650501701215218","seed":70214746752801856645732499541012355719033192755715539613510221650501701215218,"line":824,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1094644602 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1094644602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.55874968257100642998379624090890321144527163703552344952693560598847369427618","seed":55874968257100642998379624090890321144527163703552344952693560598847369427618,"line":434,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 125097598 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 125097598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"36.keymgr_stress_all_with_rand_reset.5925313425273726946024694955051328176683197208865877442993352492776719916735","seed":5925313425273726946024694955051328176683197208865877442993352492776719916735,"line":483,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 357823954 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 357823954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"39.keymgr_stress_all_with_rand_reset.66729383987370148176737665502213210573093345385925692039882544714580790889924","seed":66729383987370148176737665502213210573093345385925692039882544714580790889924,"line":913,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 520578811 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 520578811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"41.keymgr_stress_all_with_rand_reset.3579653277633972072501322551981253027688734976063707565294915517253757818611","seed":3579653277633972072501322551981253027688734976063707565294915517253757818611,"line":622,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 433579061 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 433579061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"42.keymgr_stress_all_with_rand_reset.33403369329370198223257698343324050790251186230013400741490099806774204694243","seed":33403369329370198223257698343324050790251186230013400741490099806774204694243,"line":618,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 183717719 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 183717719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.79864404305568418161170869082520483359612701725722471242209729442065853877384","seed":79864404305568418161170869082520483359612701725722471242209729442065853877384,"line":167,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 136083775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 136083775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"47.keymgr_stress_all_with_rand_reset.3472259785187587705156311291354846263814626009018426553295212456878397184586","seed":3472259785187587705156311291354846263814626009018426553295212456878397184586,"line":524,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1769751469 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1769751469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_stress_all","qual_name":"9.keymgr_stress_all.23097333708778264651463577056362065346568541616075448513207813175487368578317","seed":23097333708778264651463577056362065346568541616075448513207813175487368578317,"line":831,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2520226507 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 2520226507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_lc_disable","qual_name":"13.keymgr_lc_disable.24420898202197614337771852331684318668266126353360182156776869002064717132627","seed":24420898202197614337771852331684318668266126353360182156776869002064717132627,"line":146,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @  73045188 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000\n","UVM_INFO @  73045188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_sideload_aes","qual_name":"22.keymgr_sideload_aes.70143965824463079292151684835024137222638393426135776752742659276240001428792","seed":70143965824463079292151684835024137222638393426135776752742659276240001428792,"line":113,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_sideload_aes/latest/run.log","log_context":["UVM_ERROR @   4347837 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   4347837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_sw_invalid_input","qual_name":"41.keymgr_sw_invalid_input.69389108553559692870409700218883591298972082067270604551600717558649824335413","seed":69389108553559692870409700218883591298972082067270604551600717558649824335413,"line":279,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest/run.log","log_context":["UVM_ERROR @  42037836 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  42037836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_kmac_rsp_err","qual_name":"48.keymgr_kmac_rsp_err.53388600918005561745652524654101336364500737190985515288114364386198389025686","seed":53388600918005561745652524654101336364500737190985515288114364386198389025686,"line":97,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest/run.log","log_context":["UVM_ERROR @   4214873 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   4214873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*":[{"name":"keymgr_stress_all","qual_name":"14.keymgr_stress_all.71687257080844382926256288336432456082666499246688000741157476141476720044401","seed":71687257080844382926256288336432456082666499246688000741157476141476720044401,"line":1902,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 543790895 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1171513521 [0x45d3e0b1] vs 1171513521 [0x45d3e0b1]) reg name: keymgr_reg_block.sw_share0_output_1\n","UVM_INFO @ 543790895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_lc_disable","qual_name":"40.keymgr_lc_disable.105092025742235667374721497744598026606185190459978462370246987992990761976175","seed":105092025742235667374721497744598026606185190459978462370246987992990761976175,"line":128,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @  17528015 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3\n","UVM_INFO @  17528015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly":[{"name":"keymgr_hwsw_invalid_input","qual_name":"34.keymgr_hwsw_invalid_input.17081139134117239820314944706718566594856856845327025770180794493944870401571","seed":17081139134117239820314944706718566594856856845327025770180794493944870401571,"line":339,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest/run.log","log_context":["UVM_ERROR @ 133543605 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly\n","UVM_INFO @ 133543605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])":[{"name":"keymgr_lc_disable","qual_name":"35.keymgr_lc_disable.25875363747611521497013195124201124061815503686368248596389124882216874150451","seed":25875363747611521497013195124201124061815503686368248596389124882216874150451,"line":233,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 225426466 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6]) \n","UVM_INFO @ 225426466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"43.keymgr_stress_all_with_rand_reset.47259792194577839818683817275822186977714344844761875803077238548786159647286","seed":47259792194577839818683817275822186977714344844761875803077238548786159647286,"line":718,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 239212777 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2]) \n","UVM_INFO @ 239212777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2061,"total":2100,"percent":98.14285714285714}