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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.24291598877824862438884526023545659665051512194210182322044257660264021327402","seed":24291598877824862438884526023545659665051512194210182322044257660264021327402,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 435596009 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 435596009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"5.lc_ctrl_stress_all_with_rand_reset.86191587646733323052171312321878220832448618678836539868842024656247760347640","seed":86191587646733323052171312321878220832448618678836539868842024656247760347640,"line":952,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1615731558 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1615731558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.104094731375679129740082377130922902608590185281644624724477890275755803003256","seed":104094731375679129740082377130922902608590185281644624724477890275755803003256,"line":12577,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4846179533 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4846179533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.75968687804865819023806291770859669442747383450418341931423291368750380982447","seed":75968687804865819023806291770859669442747383450418341931423291368750380982447,"line":6108,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2690990647 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2690990647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.27610778779255388995354044060905773459057373284279580225352268507529347672130","seed":27610778779255388995354044060905773459057373284279580225352268507529347672130,"line":8703,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4973311714 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4973311714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"15.lc_ctrl_stress_all_with_rand_reset.84764403874137208566154402742188076167673074252151489580567462039637571012773","seed":84764403874137208566154402742188076167673074252151489580567462039637571012773,"line":7534,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5245529103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5245529103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.42564368024505213541763872262215570353433842725055082312695415687193396083346","seed":42564368024505213541763872262215570353433842725055082312695415687193396083346,"line":3148,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1070649234 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1070649234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.38355483497571290219632976115301712061018453408178834168443524421814700785","seed":38355483497571290219632976115301712061018453408178834168443524421814700785,"line":2018,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2047543541 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2047543541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.66909079501021198538268442926968497131117320585865943152906670748230639486824","seed":66909079501021198538268442926968497131117320585865943152906670748230639486824,"line":652,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1421980067 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1421980067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.60985735714874181043559664236798747247685360584257139925543450997522079593213","seed":60985735714874181043559664236798747247685360584257139925543450997522079593213,"line":1334,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16852479638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16852479638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.70218022990560171357521165650839679833349834816608945080912312613488034499653","seed":70218022990560171357521165650839679833349834816608945080912312613488034499653,"line":1102,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 596833712 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 596833712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.37439537827689303592633885304883343518995237909776247938602634037490761208855","seed":37439537827689303592633885304883343518995237909776247938602634037490761208855,"line":5329,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3437710179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3437710179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.96220471366275482757438967134503142717165502945271418113887779527316723395304","seed":96220471366275482757438967134503142717165502945271418113887779527316723395304,"line":11108,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13282143116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 13282143116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.25511038650980155497150690747007455220420508353282134656311940109856769716116","seed":25511038650980155497150690747007455220420508353282134656311940109856769716116,"line":3326,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5395179648 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5395179648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.103663195731429629026132570130216125127489594063080289620571211882312609390111","seed":103663195731429629026132570130216125127489594063080289620571211882312609390111,"line":4496,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1491907662 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1491907662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.79609467790837996007224301646450844492296975480779370565604415491526979003971","seed":79609467790837996007224301646450844492296975480779370565604415491526979003971,"line":8729,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4981803897 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4981803897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.85318936074029133449050935478377765003246931783704305217813721830000838513826","seed":85318936074029133449050935478377765003246931783704305217813721830000838513826,"line":1215,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 973856021 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 973856021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"38.lc_ctrl_stress_all_with_rand_reset.75167403001270295166121857390861554237771654584310272788007570575591449642360","seed":75167403001270295166121857390861554237771654584310272788007570575591449642360,"line":9657,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 989578755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 989578755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.44160652162937704850701232365864744566921735228954364263881070816147352680790","seed":44160652162937704850701232365864744566921735228954364263881070816147352680790,"line":321,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 481701301 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 481701301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.50173701957478404257305111747580910148723672252109927768089401766562989635490","seed":50173701957478404257305111747580910148723672252109927768089401766562989635490,"line":1000,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1032527542 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1032527542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.57475203165788475806753557815867923544955639799681884732570631566839569686145","seed":57475203165788475806753557815867923544955639799681884732570631566839569686145,"line":482,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 21771302460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 21771302460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.42690488475134311148950554384009426294383596576966535673120826254084272631872","seed":42690488475134311148950554384009426294383596576966535673120826254084272631872,"line":175,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2761907757 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2761907757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_jtag_errors","qual_name":"3.lc_ctrl_jtag_errors.109676816266691861683139723893686289343472227827020908018533413661249790889918","seed":109676816266691861683139723893686289343472227827020908018533413661249790889918,"line":2354,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 1914659589 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1914659589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"14.lc_ctrl_stress_all.76452161820136798246110299504433462285497962568893369682268199365303700128316","seed":76452161820136798246110299504433462285497962568893369682268199365303700128316,"line":422,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 728959761 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 728959761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"16.lc_ctrl_jtag_errors.86925325252757128876790088760467168044860885316962756573704817825326458346474","seed":86925325252757128876790088760467168044860885316962756573704817825326458346474,"line":2543,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 5035229585 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 5035229585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.19258289496373612687615414039345104541133938493326711260750142873302898535885","seed":19258289496373612687615414039345104541133938493326711260750142873302898535885,"line":3102,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 819412522 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 819412522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"42.lc_ctrl_stress_all.54675520342449702406698295032596582725929783279293068834926298670325904775854","seed":54675520342449702406698295032596582725929783279293068834926298670325904775854,"line":332,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @  73612438 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  73612438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"45.lc_ctrl_errors.90453459956037193656959310484584748013341622912735964237335377897212225664066","seed":90453459956037193656959310484584748013341622912735964237335377897212225664066,"line":1485,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 753085119 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 753085119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"49.lc_ctrl_stress_all.24425978109848710929770107337561147873060655157434903017108665686068742683174","seed":24425978109848710929770107337561147873060655157434903017108665686068742683174,"line":958,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 148566875 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 148566875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.7198217763334739193800061064351402495756254249551986206410739131464087231651","seed":7198217763334739193800061064351402495756254249551986206410739131464087231651,"line":1321,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8600191868 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked3\n","UVM_INFO @ 8600191868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2001,"total":2035,"percent":98.32923832923834}