{"block":{"name":"lc_ctrl","variant":"volatile_unlock_enabled","commit":"5ec693e5db09b2eb99805c3547847c68e0be36bf","commit_short":"5ec693e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf","revision_info":"GitHub Revision: [`5ec693e`](https://github.com/lowrisc/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-05T00:07:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/lc_ctrl_volatile_unlock_enabled/data/lc_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"lc_ctrl_smoke":{"max_time":8.2,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.28,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.46,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"lc_ctrl_csr_bit_bash":{"max_time":2.54,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"lc_ctrl_csr_aliasing":{"max_time":2.01,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"lc_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.42,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.46,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":2.01,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":130,"total":130,"percent":100.0},"V2":{"testpoints":{"state_post_trans":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.78,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"regwen_during_op":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":24.81,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rand_wr_claim_transition_if":{"tests":{"lc_ctrl_claim_transition_if":{"max_time":1.33,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_prog_failure":{"tests":{"lc_ctrl_prog_failure":{"max_time":4.09,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_state_failure":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_errors":{"tests":{"lc_ctrl_errors":{"max_time":16.44,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"security_escalation":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_prog_failure":{"max_time":4.09,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_errors":{"max_time":16.44,"sim_time":0.0,"passed":49,"total":50,"percent":98.0},"lc_ctrl_security_escalation":{"max_time":12.16,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_failure":{"max_time":48.58,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":17.19,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":93.59,"sim_time":0.0,"passed":19,"total":20,"percent":95.0}},"passed":258,"total":260,"percent":99.23076923076923},"jtag_access":{"tests":{"lc_ctrl_jtag_smoke":{"max_time":11.81,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":21.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":17.19,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":93.59,"sim_time":0.0,"passed":19,"total":20,"percent":95.0},"lc_ctrl_jtag_access":{"max_time":18.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_regwen_during_op":{"max_time":29.31,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_hw_reset":{"max_time":6.16,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_rw":{"max_time":2.57,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_bit_bash":{"max_time":20.74,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_aliasing":{"max_time":11.43,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_same_csr_outstanding":{"max_time":2.34,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_mem_rw_with_rand_reset":{"max_time":3.37,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_alert_test":{"max_time":2.64,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":209,"total":210,"percent":99.52380952380952},"jtag_priority":{"tests":{"lc_ctrl_jtag_priority":{"max_time":23.47,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_ctrl_volatile_unlock":{"tests":{"lc_ctrl_volatile_unlock_smoke":{"max_time":1.68,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"lc_ctrl_stress_all":{"max_time":372.48,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_test":{"tests":{"lc_ctrl_alert_test":{"max_time":1.7,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":4.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":4.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.28,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.46,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":2.01,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":2.05,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.28,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.46,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":2.01,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":2.05,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":985,"total":990,"percent":99.4949494949495},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"lc_ctrl_tl_intg_err":{"max_time":4.61,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":4.61,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_transition_config_regwen":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":24.81,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_manuf_state_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_manuf_state_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_state_config_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_kmac_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_local_esc":{"tests":{"lc_ctrl_state_failure":{"max_time":15.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_global_esc":{"tests":{"lc_ctrl_security_escalation":{"max_time":12.16,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_main_ctrl_flow_consistency":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.78,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":21.71,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":70,"total":70,"percent":100.0},"sec_cm_intersig_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":25.74,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_ctrl_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":25.74,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_digest":{"tests":{"lc_ctrl_sec_token_digest":{"max_time":21.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_mux_ctrl_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":17.32,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_mux_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":17.32,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":865,"total":865,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"lc_ctrl_stress_all_with_rand_reset":{"max_time":140.14,"sim_time":0.0,"passed":19,"total":50,"percent":38.0}},"passed":19,"total":50,"percent":38.0}},"passed":19,"total":50,"percent":38.0}},"coverage":{"code":{"block":null,"line_statement":97.24,"branch":94.36,"condition_expression":81.98,"toggle":89.54,"fsm":69.16},"assertion":94.13,"functional":96.26},"cov_report_page":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_jtag_errors","qual_name":"0.lc_ctrl_jtag_errors.75447066091213035133019691917324798419185759981185710552366224713978538456698","seed":75447066091213035133019691917324798419185759981185710552366224713978538456698,"line":2419,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 13763546147 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 13763546147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"9.lc_ctrl_stress_all.2883168406090046154953322066018584426486358857506129690290569986101807257675","seed":2883168406090046154953322066018584426486358857506129690290569986101807257675,"line":20215,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3315281288 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3315281288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"31.lc_ctrl_errors.11155963235386950273930143205360624545359970700532494661561619253651537726115","seed":11155963235386950273930143205360624545359970700532494661561619253651537726115,"line":2397,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 153058126 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 153058126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.6236851050566407216029791347136284234062679711992921216701827527289280090133","seed":6236851050566407216029791347136284234062679711992921216701827527289280090133,"line":1390,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 934091107 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 934091107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"0.lc_ctrl_stress_all_with_rand_reset.97524426413895842529771454258798540932294348052955071861199462998118483840412","seed":97524426413895842529771454258798540932294348052955071861199462998118483840412,"line":1596,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2880111823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2880111823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"1.lc_ctrl_stress_all_with_rand_reset.66297264053894658074559686762950463992382635305021827383619880466728775151826","seed":66297264053894658074559686762950463992382635305021827383619880466728775151826,"line":3716,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8116547784 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8116547784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.6527190357857978487800568919197334534542360467149138692117510074816014214201","seed":6527190357857978487800568919197334534542360467149138692117510074816014214201,"line":2643,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2956022884 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2956022884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"4.lc_ctrl_stress_all_with_rand_reset.75728931065687276653402821814716777233336051872673362283879583373828113656734","seed":75728931065687276653402821814716777233336051872673362283879583373828113656734,"line":450,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6270332826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6270332826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.65461480044875653031327349300788488411876924498151135407689768606633707628773","seed":65461480044875653031327349300788488411876924498151135407689768606633707628773,"line":2178,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2120848669 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2120848669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"7.lc_ctrl_stress_all_with_rand_reset.58862219332320532148519161212727964870680708557212350131773326434354499814868","seed":58862219332320532148519161212727964870680708557212350131773326434354499814868,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 645800922 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 645800922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.13327151450622244920239003697493082214311364478727418176104497875828013481635","seed":13327151450622244920239003697493082214311364478727418176104497875828013481635,"line":6112,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 18703711932 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 18703711932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.4208185595929099088809307869270307543849756809865724044321147301119192721899","seed":4208185595929099088809307869270307543849756809865724044321147301119192721899,"line":4173,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1227193500 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1227193500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.75054552684115029173597384130678784682403827726403112677085437787236659950592","seed":75054552684115029173597384130678784682403827726403112677085437787236659950592,"line":4603,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2574558880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2574558880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.90844501933621072272276691459018344991788628733676699361366334898324590245139","seed":90844501933621072272276691459018344991788628733676699361366334898324590245139,"line":12930,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17930230823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17930230823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.16079020116911709962541477049466491320393645164089418102549484366663189631537","seed":16079020116911709962541477049466491320393645164089418102549484366663189631537,"line":4226,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1952146540 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1952146540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.49425578643860862321320548931562297696267476800596555302334842565529162697139","seed":49425578643860862321320548931562297696267476800596555302334842565529162697139,"line":157,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3223693595 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3223693595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.14490495385695698269836921134849676597443829853419907422785955903791495978440","seed":14490495385695698269836921134849676597443829853419907422785955903791495978440,"line":1713,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4188859125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4188859125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.79906047016513074487783795694546286808576474036053103250672354749477165081754","seed":79906047016513074487783795694546286808576474036053103250672354749477165081754,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 105166778 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 105166778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.111818707147133149455163918380967260634606162341630033084723283863926651951088","seed":111818707147133149455163918380967260634606162341630033084723283863926651951088,"line":3554,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14097397544 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 14097397544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.32605328299307338120480915469455222262943121342177828776158060011583982031137","seed":32605328299307338120480915469455222262943121342177828776158060011583982031137,"line":1153,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 701950315 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 701950315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.80837000821477254184743200916500107820013314197341164429347299238676357660461","seed":80837000821477254184743200916500107820013314197341164429347299238676357660461,"line":1551,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17529351670 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17529351670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.20027870460844288678209592034042009800294187959541151932054478386000600755954","seed":20027870460844288678209592034042009800294187959541151932054478386000600755954,"line":7319,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2211870864 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2211870864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.44908843091759934737232117024717052631402344784975725523731143043432779789142","seed":44908843091759934737232117024717052631402344784975725523731143043432779789142,"line":803,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2326216224 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2326216224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"32.lc_ctrl_stress_all_with_rand_reset.43565766669805392715328054250928802073833786509300171884105663642428638812642","seed":43565766669805392715328054250928802073833786509300171884105663642428638812642,"line":505,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1717330328 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1717330328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.53193130420282128342530697869629531373410819394542791496564658161034867010039","seed":53193130420282128342530697869629531373410819394542791496564658161034867010039,"line":1220,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1503088615 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1503088615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.97042826183044106186549804230914545253585203103346601272245244786036513457666","seed":97042826183044106186549804230914545253585203103346601272245244786036513457666,"line":1806,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8993188306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8993188306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.90544762639270869737025771577448966760023563156886010155256903562650279612690","seed":90544762639270869737025771577448966760023563156886010155256903562650279612690,"line":1076,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1985014158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1985014158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.34780122480758440704695050180274746443416818256392529306974567120000793394125","seed":34780122480758440704695050180274746443416818256392529306974567120000793394125,"line":4631,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1643670093 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1643670093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.65461296059435481651801559154516200820913325791432638741463482208747964831271","seed":65461296059435481651801559154516200820913325791432638741463482208747964831271,"line":154,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 480991155 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 480991155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.14862885392603232465103957988798262369389060422295758900570845562366741762889","seed":14862885392603232465103957988798262369389060422295758900570845562366741762889,"line":808,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1654462631 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1654462631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.107566640101312296975287976228616025401188613549208773888076922789471771230513","seed":107566640101312296975287976228616025401188613549208773888076922789471771230513,"line":1361,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7206974152 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7206974152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.98526904067842269616285094055640015245108837149176070019116712699082359330110","seed":98526904067842269616285094055640015245108837149176070019116712699082359330110,"line":2774,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2635881901 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2635881901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"49.lc_ctrl_stress_all_with_rand_reset.99499443144630044078413269862721222666242320887617688980216719027028612095289","seed":99499443144630044078413269862721222666242320887617688980216719027028612095289,"line":1445,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2882408274 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2882408274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.57765208321224339622720529208024938809940443420814828934011385334341751475254","seed":57765208321224339622720529208024938809940443420814828934011385334341751475254,"line":9326,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16598702499 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 16598702499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1999,"total":2035,"percent":98.23095823095824}