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---\n","\n","\n"]},{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"13.otbn_passthru_mem_tl_intg_err.97824210736012056522531012029977960875285454067180686414149195774358308228543","seed":97824210736012056522531012029977960875285454067180686414149195774358308228543,"line":86,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/13.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @   4790556 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.\n","UVM_INFO @   4790556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"14.otbn_passthru_mem_tl_intg_err.113145066614651291109280766217441992720358594060275179598582822663934832302690","seed":113145066614651291109280766217441992720358594060275179598582822663934832302690,"line":96,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  52210474 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.\n","UVM_INFO @  52210474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"0.otbn_stress_all_with_rand_reset.58283164941054719484038422106318160539011872295661895478556771291937835323154","seed":58283164941054719484038422106318160539011872295661895478556771291937835323154,"line":183,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 143676234 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 143676234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"4.otbn_stress_all_with_rand_reset.56768579733965777811940139708625382316997460775175294959275192092749138420676","seed":56768579733965777811940139708625382316997460775175294959275192092749138420676,"line":172,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 1213687402 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 1213687402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"5.otbn_stress_all_with_rand_reset.28122381030522679568000037371258535788658199972693780668542782057451573126501","seed":28122381030522679568000037371258535788658199972693780668542782057451573126501,"line":205,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 1093818405 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 1093818405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.55955495998617901844367678156136242890805374010221828753796730155735761925230","seed":55955495998617901844367678156136242890805374010221828753796730155735761925230,"line":161,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 152140909 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 152140909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"3.otbn_stress_all_with_rand_reset.60957430555769631822450193012615292764185651496263386870718578232273052033805","seed":60957430555769631822450193012615292764185651496263386870718578232273052033805,"line":245,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 640133093 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 640133093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.38271033460366394320111989896970810620517312919375988151192941393283007739972","seed":38271033460366394320111989896970810620517312919375988151192941393283007739972,"line":222,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 411555600 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 411555600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_stack_addr_integ_chk","qual_name":"3.otbn_stack_addr_integ_chk.37012617770057709623043936402889942742275787787407226286132019847690288218198","seed":37012617770057709623043936402889942742275787787407226286132019847690288218198,"line":125,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25695087 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 25695087 PS) Assertion tb.model_if.NoModelErrs has failed \n","UVM_ERROR @  25695087 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  25695087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:138) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)":[{"name":"otbn_rf_base_intg_err","qual_name":"6.otbn_rf_base_intg_err.26809144187389202850099320017033760137449647017647078571300806625294244810790","seed":26809144187389202850099320017033760137449647017647078571300806625294244810790,"line":121,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log","log_context":["UVM_FATAL @  47964882 ps: (otbn_rf_base_intg_err_vseq.sv:138) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)  \n","UVM_INFO @  47964882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.81196909667907819661441413062900210181623362058745555352976632851004095224548","seed":81196909667907819661441413062900210181623362058745555352976632851004095224548,"line":165,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 112601663 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution \n","UVM_INFO @ 112601663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status":[{"name":"otbn_partial_wipe","qual_name":"8.otbn_partial_wipe.33511694749742961579119659624559772912667345354498870250606173291726534473968","seed":33511694749742961579119659624559772912667345354498870250606173291726534473968,"line":114,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log","log_context":["UVM_ERROR @   9067681 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status\n","UVM_INFO @   9067681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"otbn_single","qual_name":"96.otbn_single.57368481837029692485199331669581408328890023287929544685085028288451812362102","seed":57368481837029692485199331669581408328890023287929544685085028288451812362102,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/96.otbn_single/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}]}},"passed":1840,"total":1867,"percent":98.55382967327263}