{"block":{"name":"sram_ctrl","variant":"main","commit":"5ec693e5db09b2eb99805c3547847c68e0be36bf","commit_short":"5ec693e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf","revision_info":"GitHub Revision: [`5ec693e`](https://github.com/lowrisc/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-05T00:07:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_main/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":97.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.07,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":2.23,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.02,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":5.45,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.02,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":353.34,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":184.65,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":230,"total":230,"percent":100.0},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":1548.22,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":465.7,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":2587.13,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":1517.45,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":121.9,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":1375.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":111.68,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":605.17,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":101.53,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_partial_write":{"max_time":98.39,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_readback":{"max_time":116.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":150,"total":150,"percent":100.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1313.17,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":6.24,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":7245.17,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":1.09,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":4.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":4.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.07,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.02,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.1,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.07,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.02,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.1,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":890,"total":890,"percent":100.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":57.13,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":3.18,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":20,"total":25,"percent":80.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":3.18,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1313.17,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1313.17,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1375.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1375.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1375.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":121.9,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":9.92,"sim_time":0.0,"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":57.13,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":11.5,"sim_time":0.0,"passed":39,"total":50,"percent":78.0}},"passed":39,"total":50,"percent":78.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":97.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":97.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":1375.08,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":121.9,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":97.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.95,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0}},"passed":733,"total":780,"percent":93.97435897435898},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":180.67,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.11,"branch":98.02,"condition_expression":92.9,"toggle":90.71,"fsm":100.0},"assertion":95.83,"functional":98.14},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.71862115711198282726735037764967942103033860808239622467410531588305903078621","seed":71862115711198282726735037764967942103033860808239622467410531588305903078621,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   1724760 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   1724760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$isunknown(rdata_o))'":[{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.112645707911532811909678286606714702293722038073705815644576245077085404607744","seed":112645707911532811909678286606714702293722038073705815644576245077085404607744,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @   5224800 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @   5224800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.104939871527676912055302705295892133243729870348345726452794539151498190666670","seed":104939871527676912055302705295892133243729870348345726452794539151498190666670,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @  19189668 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @  19189668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.67621754566563710430117791435729256119450058088656331673410552723640101044480","seed":67621754566563710430117791435729256119450058088656331673410552723640101044480,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @   4678071 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @   4678071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'":[{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.115204741113655755009676723028727110782465440279781477682819838890605476079647","seed":115204741113655755009676723028727110782465440279781477682819838890605476079647,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 8262743ps failed at 8262743ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 8272844ps failed at 8272844ps\n","\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"4.sram_ctrl_readback_err.67034846876991257994711199839690427794108136173994496010557178661700252918412","seed":67034846876991257994711199839690427794108136173994496010557178661700252918412,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 1345268059 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x9)\n","UVM_INFO @ 1345268059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"5.sram_ctrl_readback_err.59956366604986483261837844146834052732951223821525519892699707948679567216026","seed":59956366604986483261837844146834052732951223821525519892699707948679567216026,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 714640399 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x71)\n","UVM_INFO @ 714640399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"9.sram_ctrl_readback_err.44306896957607512546642278760411287062247740458854372074201918948866882167530","seed":44306896957607512546642278760411287062247740458854372074201918948866882167530,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 2860239097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x70)\n","UVM_INFO @ 2860239097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"11.sram_ctrl_readback_err.12891819501241085019173598152886511991872733694867796755623657827058854232485","seed":12891819501241085019173598152886511991872733694867796755623657827058854232485,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 2765100017 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x1c)\n","UVM_INFO @ 2765100017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"22.sram_ctrl_readback_err.14511432208904755328951951059872842965170741453413620635365647466519414152392","seed":14511432208904755328951951059872842965170741453413620635365647466519414152392,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/22.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 4107229813 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x24) != exp (0x70)\n","UVM_INFO @ 4107229813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"27.sram_ctrl_readback_err.106152340334216762894415628263680266696115816483750976981942783190322795447954","seed":106152340334216762894415628263680266696115816483750976981942783190322795447954,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/27.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 1502237708 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x79) != exp (0x5)\n","UVM_INFO @ 1502237708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"35.sram_ctrl_readback_err.80909021218772615800854305815535545637143510697058146422840130193632476152090","seed":80909021218772615800854305815535545637143510697058146422840130193632476152090,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/35.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 1945881912 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x39) != exp (0x15)\n","UVM_INFO @ 1945881912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"39.sram_ctrl_readback_err.25825841978608309598964126402810397963779730215965032901180111355623935810553","seed":25825841978608309598964126402810397963779730215965032901180111355623935810553,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/39.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 662176373 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x24) != exp (0x38)\n","UVM_INFO @ 662176373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"41.sram_ctrl_readback_err.82329686613638894616592924164402825873712462826986285996798495120363606411332","seed":82329686613638894616592924164402825873712462826986285996798495120363606411332,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/41.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 684417425 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x2)\n","UVM_INFO @ 684417425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"47.sram_ctrl_readback_err.94341438370997338625111760998233588917599466197272468862053826770504363762221","seed":94341438370997338625111760998233588917599466197272468862053826770504363762221,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/47.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 658781189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x66)\n","UVM_INFO @ 658781189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"48.sram_ctrl_readback_err.19623130395687413013080953514450446793579224805665512661963890943093518924006","seed":19623130395687413013080953514450446793579224805665512661963890943093518924006,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/48.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 717591939 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x76)\n","UVM_INFO @ 717591939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"14.sram_ctrl_mubi_enc_err.104875385915991431192497082662806085816108301014167688787048783021172313414394","seed":104875385915991431192497082662806085816108301014167688787048783021172313414394,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 1583429720 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 1583429720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"18.sram_ctrl_mubi_enc_err.96094113472977751573972333140780169535078640517454257662725985351223475121550","seed":96094113472977751573972333140780169535078640517454257662725985351223475121550,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/18.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 2774865623 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 2774865623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"19.sram_ctrl_mubi_enc_err.64202837540553487985606649805691950772939648682542098035123934237174868685002","seed":64202837540553487985606649805691950772939648682542098035123934237174868685002,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/19.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 1609753062 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 1609753062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"26.sram_ctrl_mubi_enc_err.57128126540989676633410690711433676865649465700568893200790041156862051530112","seed":57128126540989676633410690711433676865649465700568893200790041156862051530112,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/26.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 707134426 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 707134426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"38.sram_ctrl_mubi_enc_err.54099637099188603240420869044746239020397095643758239308038648917624233180806","seed":54099637099188603240420869044746239020397095643758239308038648917624233180806,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/38.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 1994082340 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 1994082340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"40.sram_ctrl_mubi_enc_err.25332497618147293777320629129031745876821155111913887925109013307392841987066","seed":25332497618147293777320629129031745876821155111913887925109013307392841987066,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/40.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 2857384194 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 2857384194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":1903,"total":1950,"percent":97.58974358974359}