{"block":{"name":"sram_ctrl","variant":"ret","commit":"5ec693e5db09b2eb99805c3547847c68e0be36bf","commit_short":"5ec693e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf","revision_info":"GitHub Revision: [`5ec693e`](https://github.com/lowrisc/opentitan/tree/5ec693e5db09b2eb99805c3547847c68e0be36bf)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-05T00:07:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":101.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":1.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.03,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.31,"sim_time":0.0,"passed":19,"total":20,"percent":95.0}},"passed":19,"total":20,"percent":95.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.03,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":12.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":6.68,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":229,"total":230,"percent":99.56521739130434},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":1403.89,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":394.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":94.47,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":1300.15,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":9.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":1408.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":101.02,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":501.12,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":102.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_partial_write":{"max_time":100.2,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_readback":{"max_time":114.19,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":150,"total":150,"percent":100.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1569.78,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":1.24,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":4792.65,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":1.04,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":4.7,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":4.7,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.03,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.09,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.03,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.09,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":890,"total":890,"percent":100.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.52,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0},"sram_ctrl_tl_intg_err":{"max_time":2.79,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":25,"percent":80.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.79,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1569.78,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1569.78,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.03,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1408.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1408.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1408.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":9.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":1.6,"sim_time":0.0,"passed":45,"total":50,"percent":90.0}},"passed":45,"total":50,"percent":90.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.52,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":1.76,"sim_time":0.0,"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":101.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":101.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":1408.23,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":9.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":101.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0}},"passed":739,"total":780,"percent":94.74358974358974},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":724.29,"sim_time":0.0,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"coverage":{"code":{"block":null,"line_statement":99.07,"branch":97.98,"condition_expression":92.9,"toggle":90.66,"fsm":100.0},"assertion":95.79,"functional":98.33},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.17524952868682169982132463006791226841949148446433243782115536646884272441202","seed":17524952868682169982132463006791226841949148446433243782115536646884272441202,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   3235521 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   3235521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.19932985965659049676957603808542864585843786891421114852568617239420964247748","seed":19932985965659049676957603808542864585843786891421114852568617239420964247748,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @  15503246 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @  15503246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.53685717333557463708055406889672823697405539384164252220306618107042598197544","seed":53685717333557463708055406889672823697405539384164252220306618107042598197544,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   3271160 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   3271160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$isunknown(rdata_o))'":[{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.32681307468271815029427938956932116528688006194478102459190989841547235716401","seed":32681307468271815029427938956932116528688006194478102459190989841547235716401,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(!$isunknown(rdata_o))'\n","UVM_ERROR @   1063000 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A\n","UVM_INFO @   1063000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'":[{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.88002657363207907125220691650677645212229916242650920789416277427937341378971","seed":88002657363207907125220691650677645212229916242650920789416277427937341378971,"line":103,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 7350345ps failed at 7350345ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","UVM_ERROR @   8074327 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   8074327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"5.sram_ctrl_readback_err.23142584942583603574406140668016372943280982981751493966682729768338895132511","seed":23142584942583603574406140668016372943280982981751493966682729768338895132511,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  98624704 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x55)\n","UVM_INFO @  98624704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"7.sram_ctrl_readback_err.20797972802647804788489924182764472868278576185008286249685822316975521866576","seed":20797972802647804788489924182764472868278576185008286249685822316975521866576,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  23031191 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x33)\n","UVM_INFO @  23031191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"11.sram_ctrl_readback_err.60356524767306646194047331448168690428081445707063340621420119626721843513968","seed":60356524767306646194047331448168690428081445707063340621420119626721843513968,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  35731137 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x5b)\n","UVM_INFO @  35731137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"38.sram_ctrl_readback_err.49021887018141671691672088948444814631829310829746625081495435496709713828207","seed":49021887018141671691672088948444814631829310829746625081495435496709713828207,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/38.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  48694633 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x52)\n","UVM_INFO @  48694633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"40.sram_ctrl_readback_err.111058812715083980196462048327747511501960362356132819382674705248294890232797","seed":111058812715083980196462048327747511501960362356132819382674705248294890232797,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/40.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 105178723 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x54)\n","UVM_INFO @ 105178723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"46.sram_ctrl_readback_err.58289767565310959784069234815554670030708314056651386199503157242640046294646","seed":58289767565310959784069234815554670030708314056651386199503157242640046294646,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/46.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 105095786 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x2a)\n","UVM_INFO @ 105095786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"10.sram_ctrl_mubi_enc_err.27978014364146762934173045814217442928717249265427609358906366358876020320268","seed":27978014364146762934173045814217442928717249265427609358906366358876020320268,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  28527702 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  28527702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"35.sram_ctrl_mubi_enc_err.8361306897947086833890854117551306355677855901334328603324507722488062771319","seed":8361306897947086833890854117551306355677855901334328603324507722488062771319,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  65281699 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  65281699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"37.sram_ctrl_mubi_enc_err.82664858859568135382551962981866574100450125429468470457957223251147642291654","seed":82664858859568135382551962981866574100450125429468470457957223251147642291654,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  45437593 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  45437593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"40.sram_ctrl_mubi_enc_err.5641158398322726450541521674154162623110981684294531295756541517116422454410","seed":5641158398322726450541521674154162623110981684294531295756541517116422454410,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  27021119 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  27021119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"43.sram_ctrl_mubi_enc_err.91313584596600626234741742229105979312347516807110808639123237905479534128980","seed":91313584596600626234741742229105979312347516807110808639123237905479534128980,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  99330063 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  99330063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"39.sram_ctrl_stress_all_with_rand_reset.8237028592785437211379321247455982881834800001084049804423071558235740039224","seed":8237028592785437211379321247455982881834800001084049804423071558235740039224,"line":160,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 993636700 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 993636700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"45.sram_ctrl_stress_all_with_rand_reset.37895917588549567961543502972204293845036926297089745227957461895874592179002","seed":37895917588549567961543502972204293845036926297089745227957461895874592179002,"line":165,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8160896453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8160896453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"2.sram_ctrl_csr_mem_rw_with_rand_reset.115784247847699139431580925012331717788047188706587060461873992924832522531991","seed":115784247847699139431580925012331717788047188706587060461873992924832522531991,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  91797452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 \n","UVM_INFO @  91797452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1906,"total":1950,"percent":97.74358974358974}