{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"4a305de5bc41babedc480ac19fa1f67c26b17362","commit_short":"4a305de","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/4a305de5bc41babedc480ac19fa1f67c26b17362","revision_info":"GitHub Revision: [`4a305de`](https://github.com/lowrisc/opentitan/tree/4a305de5bc41babedc480ac19fa1f67c26b17362)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-12T00:11:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":3.26,"sim_time":10237.526521,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"8.rstmgr_cnsty_chk_test.90608255746954979063282644105926634385238570386287900821964424296229589676266","seed":90608255746954979063282644105926634385238570386287900821964424296229589676266,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/8.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1800283004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1818203004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1836123004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1854043004 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"9.rstmgr_cnsty_chk_test.49682823393050940157792200334273994424253958323764512930078212000649419353096","seed":49682823393050940157792200334273994424253958323764512930078212000649419353096,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1752187187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1769627187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1787067187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1804507187 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":8,"total":10,"percent":80.0}