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[`4a305de`](https://github.com/lowrisc/opentitan/tree/4a305de5bc41babedc480ac19fa1f67c26b17362)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-12T00:11:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":473.15,"sim_time":120952.868921,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.84,"sim_time":72.50201799999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":3.37,"sim_time":355.108205,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":31.75,"sim_time":6462.547377000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":25.1,"sim_time":3762.933827,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":4.47,"sim_time":180.578843,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":3.37,"sim_time":355.108205,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":25.1,"sim_time":3762.933827,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":1.04,"sim_time":13.073837,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":2.26,"sim_time":75.171364,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":115,"total":115,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.24,"sim_time":23.95709,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.1,"sim_time":2.4279349999999997,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":1.08,"sim_time":3.805211,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":7.61,"sim_time":486.75013,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":7.61,"sim_time":486.75013,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":28.11,"sim_time":8197.886803,"passed":50,"total":50,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.5,"sim_time":364.218696,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":35.79,"sim_time":28710.592857,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":36.01,"sim_time":44523.723538000006,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":29.48,"sim_time":21795.150032,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":29.48,"sim_time":21795.150032,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":41.35,"sim_time":4389.605666,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":41.35,"sim_time":4389.605666,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":41.35,"sim_time":4389.605666,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":41.35,"sim_time":4389.605666,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":41.35,"sim_time":4389.605666,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":45.77,"sim_time":89746.340499,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":87.85,"sim_time":18997.499563999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":87.85,"sim_time":18997.499563999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":87.85,"sim_time":18997.499563999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":51.97,"sim_time":4490.793833,"passed":50,"total":50,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":14.03,"sim_time":23531.954752999998,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":87.85,"sim_time":18997.499563999998,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":290.85,"sim_time":57456.275542999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":14.93,"sim_time":10828.486076,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":14.93,"sim_time":10828.486076,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":473.15,"sim_time":120952.868921,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":417.99,"sim_time":251021.215475,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":665.79,"sim_time":378751.786726,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.13,"sim_time":14.0451,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.17,"sim_time":14.594583,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":5.96,"sim_time":451.14913900000005,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":5.96,"sim_time":451.14913900000005,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.84,"sim_time":72.50201799999999,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":3.37,"sim_time":355.108205,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":25.1,"sim_time":3762.933827,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.64,"sim_time":160.895757,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.84,"sim_time":72.50201799999999,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":3.37,"sim_time":355.108205,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":25.1,"sim_time":3762.933827,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.64,"sim_time":160.895757,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1020,"total":1041,"percent":97.98270893371757},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.73,"sim_time":107.287319,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":21.61,"sim_time":1043.398242,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":21.61,"sim_time":1043.398242,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":370.33,"sim_time":278420.477199,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.1,"branch":98.4,"condition_expression":96.57,"toggle":83.54,"fsm":89.36},"assertion":94.76,"functional":99.26},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.90805874382714871359494738551949610702125247874690754565380362024753561194949","seed":90805874382714871359494738551949610702125247874690754565380362024753561194949,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3964600 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3964600 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[911])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.8901338201460552755319150487668712328903353911652008700364122844679011892479","seed":8901338201460552755319150487668712328903353911652008700364122844679011892479,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2052941 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2052941 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[899])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.74178580353849676024748120782030338647926686874411627665841084766097530998386","seed":74178580353849676024748120782030338647926686874411627665841084766097530998386,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    909614 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    909614 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[922])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.43386983585795802996333490212853523217018460262567495330961461919114443612737","seed":43386983585795802996333490212853523217018460262567495330961461919114443612737,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    921836 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    921836 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.40142227909620720996165132567656498112479704997587068282256873961071377640953","seed":40142227909620720996165132567656498112479704997587068282256873961071377640953,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1867626 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1867626 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[972])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.40045706508941202929306204874368495965298253544687931912624932977803078587265","seed":40045706508941202929306204874368495965298253544687931912624932977803078587265,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  12472361 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  12472361 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.24698725095567769514285800254555377254547224923422044070562507936606389248822","seed":24698725095567769514285800254555377254547224923422044070562507936606389248822,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    812020 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    812020 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[978])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.12834514323473354448565047689079558557911881899480700891463656887339975656713","seed":12834514323473354448565047689079558557911881899480700891463656887339975656713,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    982158 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    982158 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.99562322247275158731522888907713655217447024628615683240216661766705276892605","seed":99562322247275158731522888907713655217447024628615683240216661766705276892605,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1809122 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1809122 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.33547443903004040472000777174567764900379066776052432651038836392902180336235","seed":33547443903004040472000777174567764900379066776052432651038836392902180336235,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1145079 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1145079 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[961])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.63609253946090390580581655917560190318096346243624516974154690235280121425653","seed":63609253946090390580581655917560190318096346243624516974154690235280121425653,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3183334 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3183334 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.21355498456559878426908588542493863974619346746894816266409266500914600388362","seed":21355498456559878426908588542493863974619346746894816266409266500914600388362,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    739791 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    739791 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.55396242853858345644733003723062805157402043775182182032907535578516921265958","seed":55396242853858345644733003723062805157402043775182182032907535578516921265958,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3901699 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3901699 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.5442385683232836599638579758913089286747791916611111721576460537172324980870","seed":5442385683232836599638579758913089286747791916611111721576460537172324980870,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1232677 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1232677 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.3465932154239244142386728729311774130491351251173489506029862555320871961807","seed":3465932154239244142386728729311774130491351251173489506029862555320871961807,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3019724 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3019724 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[971])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.104666232215124723804535674311332165357785170209429239168725307688894173311193","seed":104666232215124723804535674311332165357785170209429239168725307688894173311193,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3125175 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3125175 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[902])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.44004547082475989840152851628349733574866667157702666247625840591313295533557","seed":44004547082475989840152851628349733574866667157702666247625840591313295533557,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    882281 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    882281 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.19716912737790226099595659032285671790474248235387611566593552266147021913195","seed":19716912737790226099595659032285671790474248235387611566593552266147021913195,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1198496 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1198496 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.58116446761149774575366962075455517066990576426201718680388302251306382666736","seed":58116446761149774575366962075455517066990576426201718680388302251306382666736,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   6615929 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   6615929 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[932])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.70439881293733974208227919079240664175295025679025173409962697158135580885309","seed":70439881293733974208227919079240664175295025679025173409962697158135580885309,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4872097 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4872097 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[906])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.37157422465862982696961913173268680479265061353419525459299982326942613737664","seed":37157422465862982696961913173268680479265061353419525459299982326942613737664,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1086211 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf8e91 [101011111000111010010001] vs 0x0 [0]) \n","UVM_ERROR @   1148211 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6d17c3 [11011010001011111000011] vs 0x0 [0]) \n","UVM_ERROR @   1234211 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf438a0 [111101000011100010100000] vs 0x0 [0]) \n","UVM_ERROR @   1286211 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55fcb [1010101111111001011] vs 0x0 [0]) \n"]}]}},"passed":1130,"total":1151,"percent":98.17549956559513}