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[`4a305de`](https://github.com/lowrisc/opentitan/tree/4a305de5bc41babedc480ac19fa1f67c26b17362)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-12T00:11:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":9.13,"sim_time":2110.705709,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":10.26,"sim_time":2464.035861,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":6.8,"sim_time":2185.9368569999997,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":8.67,"sim_time":2313.5081,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":14.86,"sim_time":6017.50266,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.63,"sim_time":2035.2937960000004,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":164.3,"sim_time":44133.291183,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":10.61,"sim_time":2575.108014,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":9.22,"sim_time":2073.530486,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.63,"sim_time":2035.2937960000004,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":10.61,"sim_time":2575.108014,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":165,"total":165,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":501.4100000000001,"sim_time":157292.442469,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":657.68,"sim_time":283711.542201,"passed":96,"total":100,"percent":96.0}},"passed":96,"total":100,"percent":96.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":550.15,"sim_time":265033.530257,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":838.38,"sim_time":645217.3464800001,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":9.47,"sim_time":2510.300655,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.6,"sim_time":2040.344179,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":465.88,"sim_time":683224.134354,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":9.93,"sim_time":2608.732603,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":386.13,"sim_time":2535364.090423,"passed":43,"total":50,"percent":86.0}},"passed":43,"total":50,"percent":86.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":128.14,"sim_time":42005.832697,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":3139.93,"sim_time":1239764.363924,"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":8.1,"sim_time":2010.4293219999997,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.56,"sim_time":2012.2255,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.79,"sim_time":2116.7335,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.79,"sim_time":2116.7335,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":14.86,"sim_time":6017.50266,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.63,"sim_time":2035.2937960000004,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":10.61,"sim_time":2575.108014,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":46.24,"sim_time":9714.247456000001,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":14.86,"sim_time":6017.50266,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.63,"sim_time":2035.2937960000004,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":10.61,"sim_time":2575.108014,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":46.24,"sim_time":9714.247456000001,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":705,"total":722,"percent":97.64542936288089},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":103.06,"sim_time":42006.950841,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":87.95,"sim_time":42425.05245,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":87.95,"sim_time":42425.05245,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":26.97,"sim_time":8873.336927999999,"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0}},"coverage":{"code":{"block":null,"line_statement":98.92,"branch":99.0,"condition_expression":98.04,"toggle":100.0,"fsm":93.59},"assertion":98.28,"functional":86.17},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *":[{"name":"sysrst_ctrl_ec_pwr_on_rst","qual_name":"1.sysrst_ctrl_ec_pwr_on_rst.57803708691733251253507008794647599354470209635318864727138196571838771902137","seed":57803708691733251253507008794647599354470209635318864727138196571838771902137,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest/run.log","log_context":["UVM_INFO @ 2316196396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"12.sysrst_ctrl_stress_all_with_rand_reset.26836290669466740088509549303477970611499341523050629457899518456702869997386","seed":26836290669466740088509549303477970611499341523050629457899518456702869997386,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 4507694847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"6.sysrst_ctrl_ultra_low_pwr.27907395506166968018761934629494993329657805634744421181327324495190101230596","seed":27907395506166968018761934629494993329657805634744421181327324495190101230596,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 6355790810 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 6355790810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"11.sysrst_ctrl_ultra_low_pwr.745655100657915301532255926882364317878597637006238545524182518295589570078","seed":745655100657915301532255926882364317878597637006238545524182518295589570078,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4722199442 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4722199442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"24.sysrst_ctrl_ultra_low_pwr.60020630823325760131944752656614628850087859442146710478244780500752741358187","seed":60020630823325760131944752656614628850087859442146710478244780500752741358187,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3118420932 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3118420932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"26.sysrst_ctrl_stress_all.99932514560139857047525553250106270926076880177654015085664693661853038405507","seed":99932514560139857047525553250106270926076880177654015085664693661853038405507,"line":674,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 14988138292 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 14988138292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"31.sysrst_ctrl_edge_detect.91135820550296438377299176904461328914889177182324266757161088167547404988355","seed":91135820550296438377299176904461328914889177182324266757161088167547404988355,"line":678,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4156883524 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4156883524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"40.sysrst_ctrl_edge_detect.22317145640585764523145087758330302727386986655373313725233538456766296928937","seed":22317145640585764523145087758330302727386986655373313725233538456766296928937,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2976865132 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2976865132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"44.sysrst_ctrl_ultra_low_pwr.84505133289431743178374571872847162087476591907308962942061323080789787404882","seed":84505133289431743178374571872847162087476591907308962942061323080789787404882,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5886044591 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5886044591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"48.sysrst_ctrl_ultra_low_pwr.107092432452803591831865095750875541940785897188231873933984894924542586073773","seed":107092432452803591831865095750875541940785897188231873933984894924542586073773,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4008227960 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4008227960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"49.sysrst_ctrl_ultra_low_pwr.112835339818238971841494020983908406004958868411648962032241457972339032086681","seed":112835339818238971841494020983908406004958868411648962032241457972339032086681,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4805281256 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4805281256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_stress_all","qual_name":"14.sysrst_ctrl_stress_all.18520891370088609652447177033610311965808861937440580998227141026734823862016","seed":18520891370088609652447177033610311965808861937440580998227141026734823862016,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 7129642435 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 7654642435 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7661044554 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq\n","UVM_INFO @ 9659660591 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"35.sysrst_ctrl_ultra_low_pwr.645812483470929644687624720996813077484953901410599266198224923125866183675","seed":645812483470929644687624720996813077484953901410599266198224923125866183675,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2357901249 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_ERROR @ 3663558729 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 3663558729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"40.sysrst_ctrl_stress_all.29276006582643820473892392501114061245941405767387611697046472045032962392604","seed":29276006582643820473892392501114061245941405767387611697046472045032962392604,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 4498878315 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 6348878315 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 6356789414 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq\n","UVM_INFO @ 8353894986 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq\n"]}],"UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*])":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"22.sysrst_ctrl_stress_all_with_rand_reset.58220604095384904448903188789072692451952415032550447107793292153659196309645","seed":58220604095384904448903188789072692451952415032550447107793292153659196309645,"line":735,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11995818578 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 11995818578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"45.sysrst_ctrl_stress_all_with_rand_reset.84788729034601373990120467960025824217303678394843265771070911574191653677393","seed":84788729034601373990120467960025824217303678394843265771070911574191653677393,"line":680,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6781432732 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 6781432732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"56.sysrst_ctrl_combo_detect_with_pre_cond.108009650491977367463003629895410432761163980122535337799971779646402468491958","seed":108009650491977367463003629895410432761163980122535337799971779646402468491958,"line":683,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 63724635148 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f\n","UVM_INFO @ 63724657370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32\n","UVM_INFO @ 66204254796 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2\n","UVM_INFO @ 66219163455 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"99.sysrst_ctrl_combo_detect_with_pre_cond.59238385092217198111114114508435819141126341531286707338720060880076342209945","seed":59238385092217198111114114508435819141126341531286707338720060880076342209945,"line":685,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 45898908002 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 45898908002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"59.sysrst_ctrl_combo_detect_with_pre_cond.59331107450212882575270962554820439746729015179819408125574804143112897893397","seed":59331107450212882575270962554820439746729015179819408125574804143112897893397,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 13413704458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 13433704458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 23519981005 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x24\n","UVM_INFO @ 23520041611 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x14\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"64.sysrst_ctrl_combo_detect_with_pre_cond.8522789615778409112426388987956189958451213239205189957984238189700410790174","seed":8522789615778409112426388987956189958451213239205189957984238189700410790174,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 15950321318 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.intr_state reset value: 0x0 \n","UVM_INFO @ 15950321318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":912,"total":932,"percent":97.85407725321889}